diff mbox series

arm64: dts: rockchip: Add vop for rk3576

Message ID 20241209122943.2781431-2-andyshrk@163.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: rockchip: Add vop for rk3576 | expand

Commit Message

Andy Yan Dec. 9, 2024, 12:29 p.m. UTC 
From: Andy Yan <andy.yan@rock-chips.com>

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 70 +++++++++++++++++++++++-
 1 file changed, 69 insertions(+), 1 deletion(-)

Comments

Andy Yan Dec. 9, 2024, 12:36 p.m. UTC | #1 
Sorry, please ignore this patch.

At 2024-12-09 20:29:11, "Andy Yan" <andyshrk@163.com> wrote:
>From: Andy Yan <andy.yan@rock-chips.com>
>
>Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
>---
> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 70 +++++++++++++++++++++++-
> 1 file changed, 69 insertions(+), 1 deletion(-)
>
>diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
>index 70ddedb0c890..45823a758b6e 100644
>--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
>+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
>@@ -393,6 +393,11 @@ opp-950000000 {
> 		};
> 	};
> 
>+	display_subsystem: display-subsystem {
>+		compatible = "rockchip,display-subsystem";
>+		ports = <&vop_out>;
>+	};
>+
> 	firmware {
> 		scmi: scmi {
> 			compatible = "arm,scmi-smc";
>@@ -832,6 +837,70 @@ gpu: gpu@27800000 {
> 			status = "disabled";
> 		};
> 
>+		vop: vop@27d00000 {
>+			compatible = "rockchip,rk3576-vop";
>+			reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
>+			reg-names = "vop", "gamma-lut";
>+			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>+				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
>+				     <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
>+				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
>+			interrupt-names = "vop-sys",
>+					  "vop-vp0",
>+					  "vop-vp1",
>+					  "vop-vp2";
>+			clocks = <&cru ACLK_VOP>,
>+				 <&cru HCLK_VOP>,
>+				 <&cru DCLK_VP0>,
>+				 <&cru DCLK_VP1>,
>+				 <&cru DCLK_VP2>;
>+			clock-names = "aclk",
>+				      "hclk",
>+				      "dclk_vp0",
>+				      "dclk_vp1",
>+				      "dclk_vp2";
>+			iommus = <&vop_mmu>;
>+			power-domains = <&power RK3576_PD_VOP>;
>+			rockchip,grf = <&sys_grf>;
>+			rockchip,pmu = <&pmu>;
>+			status = "disabled";
>+
>+			vop_out: ports {
>+				#address-cells = <1>;
>+				#size-cells = <0>;
>+
>+				vp0: port@0 {
>+					#address-cells = <1>;
>+					#size-cells = <0>;
>+					reg = <0>;
>+				};
>+
>+				vp1: port@1 {
>+					#address-cells = <1>;
>+					#size-cells = <0>;
>+					reg = <1>;
>+				};
>+
>+				vp2: port@2 {
>+					#address-cells = <1>;
>+					#size-cells = <0>;
>+					reg = <2>;
>+				};
>+			};
>+		};
>+
>+		vop_mmu: iommu@27d07e00 {
>+			compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
>+			reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
>+			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
>+			interrupt-names = "vop_mmu";
>+			clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
>+			clock-names = "aclk", "iface";
>+			#iommu-cells = <0>;
>+			power-domains = <&power RK3576_PD_VOP>;
>+			status = "disabled";
>+		};
>+
> 		hdmi: hdmi@27da0000 {
> 			compatible = "rockchip,rk3576-dw-hdmi-qp";
> 			reg = <0x0 0x27da0000 0x0 0x20000>;
>@@ -873,7 +942,6 @@ hdmi_out: port@1 {
> 			};
> 		};
> 
>->>>>>>> 2b62c69b3a4c (arm64: dts: rockchip: Add hdmi for rk3576)
> 		qos_hdcp1: qos@27f02000 {
> 			compatible = "rockchip,rk3576-qos", "syscon";
> 			reg = <0x0 0x27f02000 0x0 0x20>;
>-- 
>2.34.1
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 70ddedb0c890..45823a758b6e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -393,6 +393,11 @@  opp-950000000 {
 		};
 	};
 
+	display_subsystem: display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+	};
+
 	firmware {
 		scmi: scmi {
 			compatible = "arm,scmi-smc";
@@ -832,6 +837,70 @@  gpu: gpu@27800000 {
 			status = "disabled";
 		};
 
+		vop: vop@27d00000 {
+			compatible = "rockchip,rk3576-vop";
+			reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
+			reg-names = "vop", "gamma-lut";
+			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "vop-sys",
+					  "vop-vp0",
+					  "vop-vp1",
+					  "vop-vp2";
+			clocks = <&cru ACLK_VOP>,
+				 <&cru HCLK_VOP>,
+				 <&cru DCLK_VP0>,
+				 <&cru DCLK_VP1>,
+				 <&cru DCLK_VP2>;
+			clock-names = "aclk",
+				      "hclk",
+				      "dclk_vp0",
+				      "dclk_vp1",
+				      "dclk_vp2";
+			iommus = <&vop_mmu>;
+			power-domains = <&power RK3576_PD_VOP>;
+			rockchip,grf = <&sys_grf>;
+			rockchip,pmu = <&pmu>;
+			status = "disabled";
+
+			vop_out: ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				vp0: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+				};
+
+				vp1: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+				};
+
+				vp2: port@2 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <2>;
+				};
+			};
+		};
+
+		vop_mmu: iommu@27d07e00 {
+			compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+			reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
+			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "vop_mmu";
+			clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+			clock-names = "aclk", "iface";
+			#iommu-cells = <0>;
+			power-domains = <&power RK3576_PD_VOP>;
+			status = "disabled";
+		};
+
 		hdmi: hdmi@27da0000 {
 			compatible = "rockchip,rk3576-dw-hdmi-qp";
 			reg = <0x0 0x27da0000 0x0 0x20000>;
@@ -873,7 +942,6 @@  hdmi_out: port@1 {
 			};
 		};
 
->>>>>>> 2b62c69b3a4c (arm64: dts: rockchip: Add hdmi for rk3576)
 		qos_hdcp1: qos@27f02000 {
 			compatible = "rockchip,rk3576-qos", "syscon";
 			reg = <0x0 0x27f02000 0x0 0x20>;