| Message ID | 20241210-tianma_tm070jdhg34-v1-2-9fb7fe6b6cf0@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/panel: simple: Add Tianma TM070JDHG34-00 DT bindings and driver support | expand |
On 10/12/2024 18:28, Luca Ceresoli wrote: > Add Tianma TM070JDHG34-00 7.0" 1280x800 LVDS RGB TFT LCD panel. > > Panel info and datasheet: https://fortec.us/products/tm070jdhg34-00/ > > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > --- > drivers/gpu/drm/panel/panel-simple.c | 42 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c > index 1562f122724137dec37eb11443eafc896ef2f2e8..b3c931a4e46a2568b3678d664f11b189873fa1e2 100644 > --- a/drivers/gpu/drm/panel/panel-simple.c > +++ b/drivers/gpu/drm/panel/panel-simple.c > @@ -4286,6 +4286,45 @@ static const struct panel_desc tianma_tm070jvhg33 = { > .bus_flags = DRM_BUS_FLAG_DE_HIGH, > }; > > +/* > + * The datasheet computes total blanking as back porch + front porch, not > + * including sync pulse width. This is for both H and V. To make the total > + * blanking and period correct, subtract the pulse width from the front > + * porch. > + * > + * This works well for the Min and Typ values, but for Max values the sync > + * pulse width is higher than back porch + front porch, so work around that > + * by reducing the Max sync length value to 1 and then treating the Max > + * porches as in the Min and Typ cases. > + * > + * Exact datasheet values are added as a comment where they differ from the > + * ones implemented for the above reason. > + */ > +static const struct display_timing tianma_tm070jdhg34_00_timing = { > + .pixelclock = { 68400000, 71900000, 78100000 }, > + .hactive = { 1280, 1280, 1280 }, > + .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ > + .hback_porch = { 5, 5, 5 }, > + .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ > + .vactive = { 800, 800, 800 }, > + .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ > + .vback_porch = { 2, 2, 2 }, > + .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ > + .flags = DISPLAY_FLAGS_DE_HIGH, > +}; > + > +static const struct panel_desc tianma_tm070jdhg34_00 = { > + .timings = &tianma_tm070jdhg34_00_timing, > + .num_timings = 1, > + .bpc = 8, > + .size = { > + .width = 150, /* 149.76 */ > + .height = 94, /* 93.60 */ > + }, > + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, > + .connector_type = DRM_MODE_CONNECTOR_LVDS, > +}; > + > static const struct display_timing tianma_tm070rvhg71_timing = { > .pixelclock = { 27700000, 29200000, 39600000 }, > .hactive = { 800, 800, 800 }, > @@ -5028,6 +5067,9 @@ static const struct of_device_id platform_of_match[] = { > }, { > .compatible = "tianma,tm070jdhg30", > .data = &tianma_tm070jdhg30, > + }, { > + .compatible = "tianma,tm070jdhg34-00", > + .data = &tianma_tm070jdhg34_00, > }, { > .compatible = "tianma,tm070jvhg33", > .data = &tianma_tm070jvhg33, > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 1562f122724137dec37eb11443eafc896ef2f2e8..b3c931a4e46a2568b3678d664f11b189873fa1e2 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -4286,6 +4286,45 @@ static const struct panel_desc tianma_tm070jvhg33 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH, }; +/* + * The datasheet computes total blanking as back porch + front porch, not + * including sync pulse width. This is for both H and V. To make the total + * blanking and period correct, subtract the pulse width from the front + * porch. + * + * This works well for the Min and Typ values, but for Max values the sync + * pulse width is higher than back porch + front porch, so work around that + * by reducing the Max sync length value to 1 and then treating the Max + * porches as in the Min and Typ cases. + * + * Exact datasheet values are added as a comment where they differ from the + * ones implemented for the above reason. + */ +static const struct display_timing tianma_tm070jdhg34_00_timing = { + .pixelclock = { 68400000, 71900000, 78100000 }, + .hactive = { 1280, 1280, 1280 }, + .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ + .hback_porch = { 5, 5, 5 }, + .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ + .vactive = { 800, 800, 800 }, + .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ + .vback_porch = { 2, 2, 2 }, + .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc tianma_tm070jdhg34_00 = { + .timings = &tianma_tm070jdhg34_00_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 150, /* 149.76 */ + .height = 94, /* 93.60 */ + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + static const struct display_timing tianma_tm070rvhg71_timing = { .pixelclock = { 27700000, 29200000, 39600000 }, .hactive = { 800, 800, 800 }, @@ -5028,6 +5067,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "tianma,tm070jdhg30", .data = &tianma_tm070jdhg30, + }, { + .compatible = "tianma,tm070jdhg34-00", + .data = &tianma_tm070jdhg34_00, }, { .compatible = "tianma,tm070jvhg33", .data = &tianma_tm070jvhg33,
Add Tianma TM070JDHG34-00 7.0" 1280x800 LVDS RGB TFT LCD panel. Panel info and datasheet: https://fortec.us/products/tm070jdhg34-00/ Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> --- drivers/gpu/drm/panel/panel-simple.c | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)