| Message ID | 20241213184705.317138-1-eric.smith@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: add modifiers for MediaTek tiled formats | expand |
Hi Eric, On Fri, 13 Dec 2024 at 18:47, <eric.smith@collabora.com> wrote: > MediaTek (MTK) uses some unique tiled memory formats > for video decoding. Add these to the uapi drm_fourcc.h > so that we can use them in Mesa, GStreamer, and other > tools/libraries. Thanks for pushing these upstream! > +/* MediaTek layouts */ > + > +/* > + * MediaTek Tiled Modifier > + * This is a tiled layout using tiles of 16x32 pixels in a row-major layout. > + * For chroma planes this becomes 16x16 tiles. > + */ > +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE fourcc_mod_code(MTK, (1ULL << 0)) I think this probably wants to be something like the tiling mode defined in AMD/Arm modifiers, i.e. reserve a few bits in the range to select the tile size, rather than using a single bit here. > +/* > + * MediaTek Compressed Modifier > + * Indicates the planes are compressed. > + * Implementation may be platform and base-format specific. > + */ > +#define DRM_FORMAT_MOD_MTK_COMPRESSED fourcc_mod_code(MTK, (1ULL << 1)) Ditto for compression. > +/* > + * MediaTek 10-bit Modifier > + * Indicates that the 2 LSBs of the 10 bit pixels are stored > + * separately and tiled. > + */ > +#define DRM_FORMAT_MOD_MTK_LSBTILED fourcc_mod_code(MTK, (1ULL << 2)) > + > +/* > + * MediaTek 10-bit Modifier > + * Indicates that the 2 LSBs of 10 bit pixels are stored > + * separately in raster order. > + */ > +#define DRM_FORMAT_MOD_MTK_LSBRASTER fourcc_mod_code(MTK, (1ULL << 3)) Ditto for 10bpc packing. So this would ultimately look something like: mod = (DRM_FORMAT_MOD_MTK_TILE_SIZE(16L32S) | DRM_FORMAT_MOD_MTK_COMPRESSION(V1) | DRM_FORMAT_MOD_MTK_10BPC_PACK(RASTER)) Cheers, Daniel
On 18/12/2024 10.33, Daniel Stone wrote: >> +/* MediaTek layouts */ >> + >> +/* >> + * MediaTek Tiled Modifier >> + * This is a tiled layout using tiles of 16x32 pixels in a row-major layout. >> + * For chroma planes this becomes 16x16 tiles. >> + */ >> +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE fourcc_mod_code(MTK, (1ULL << 0)) > I think this probably wants to be something like the tiling mode > defined in AMD/Arm modifiers, i.e. reserve a few bits in the range to > select the tile size, rather than using a single bit here. Thank you for taking the time, and for your suggestions. Are you thinking something along the lines of: /* MediaTek modifiers * Bits Parameter Notes * ----- ------------------------ --------------------------------------------- * 3:0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* * 7:4 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* * 12:8 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* * */ #define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) /* * MediaTek Tiled Modifier * The lowest 4 bits of the modifier is used to specify the tiling * layout. Only the 16L_32S tiling is used for now, but we define an * "untiled" version and leave room for future expansion. */ #define MTK_FMT_MOD_TILE_MASK 0xf #define MTK_FMT_MOD_TILE_NONE 0x0 #define MTK_FMT_MOD_TILE_16L32S 0x1 /* * Bits 4-7 specify compression options */ #define MTK_FMT_MOD_COMPRESS_MASK (0xf << 4) #define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 4) #define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 4) /* * Bits 8-11 specify how the bits of 10 bit formats are * stored out in memory */ #define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 8) #define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 8) #define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 8) #define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 8) Regards, Eric
Hey Eric, On Thu, 19 Dec 2024 at 00:20, Eric Smith <eric.smith@collabora.com> wrote: > On 18/12/2024 10.33, Daniel Stone wrote: > >> +/* > >> + * MediaTek Tiled Modifier > >> + * This is a tiled layout using tiles of 16x32 pixels in a row-major layout. > >> + * For chroma planes this becomes 16x16 tiles. > >> + */ > >> +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE fourcc_mod_code(MTK, (1ULL << 0)) > > I think this probably wants to be something like the tiling mode > > defined in AMD/Arm modifiers, i.e. reserve a few bits in the range to > > select the tile size, rather than using a single bit here. > > Thank you for taking the time, and for your suggestions. Are you > thinking something along the lines of: > > [...] Yeah, that's exactly it. You could even push the boat out and widen the fields a little bit to give more headroom; if you want to change the layout because you want to add more flags or whatever, you can just do what Arm did, and take the top couple of bits as a layout version or epoch. Cheers, Daniel
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 70f3b00b0681..22a27cdd6484 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -421,6 +421,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b /* add more to the end as needed */ @@ -1453,6 +1454,36 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) +/* MediaTek layouts */ + +/* + * MediaTek Tiled Modifier + * This is a tiled layout using tiles of 16x32 pixels in a row-major layout. + * For chroma planes this becomes 16x16 tiles. + */ +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE fourcc_mod_code(MTK, (1ULL << 0)) + +/* + * MediaTek Compressed Modifier + * Indicates the planes are compressed. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_MTK_COMPRESSED fourcc_mod_code(MTK, (1ULL << 1)) + +/* + * MediaTek 10-bit Modifier + * Indicates that the 2 LSBs of the 10 bit pixels are stored + * separately and tiled. + */ +#define DRM_FORMAT_MOD_MTK_LSBTILED fourcc_mod_code(MTK, (1ULL << 2)) + +/* + * MediaTek 10-bit Modifier + * Indicates that the 2 LSBs of 10 bit pixels are stored + * separately in raster order. + */ +#define DRM_FORMAT_MOD_MTK_LSBRASTER fourcc_mod_code(MTK, (1ULL << 3)) + /* * AMD modifiers *