| Message ID | 20250106-add-writeback-support-for-sm6150-v1-1-1d2d69fc4bae@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dpu: Add writeback support for SM6150 | expand |
On Mon, Jan 06, 2025 at 02:39:09PM +0800, Fange Zhang wrote: > On the SM6150 platform there is WB_2 block. Add it to the SM6150 catalog. > > Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> > --- > A followup patch to add writeback configuration for the SM6150 catalog > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 1/5/2025 10:39 PM, Fange Zhang wrote: > On the SM6150 platform there is WB_2 block. Add it to the SM6150 catalog. > > Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> > --- > A followup patch to add writeback configuration for the SM6150 catalog > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > index 621a2140f675fa28b3a7fcd8573e59b306cd6832..6d32deead77728264b6de6d5fd2843a81afdf355 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > @@ -27,6 +27,7 @@ static const struct dpu_mdp_cfg sm6150_mdp = { > [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, > [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, > [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, > + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, > }, > }; > > @@ -164,6 +165,21 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = { > }, > }; > > +static const struct dpu_wb_cfg sm6150_wb[] = { > + { > + .name = "wb_2", .id = WB_2, > + .base = 0x66000, .len = 0x2c8, This is not correct. WB_2 offset is at 0x66000. However, MDP base address accounts for the 0x1000 offset. So this should still be 0x65000. Why is 0x66000 used here? It does not match the docs. How was this change verified? > + .features = WB_SM8250_MASK, > + .format_list = wb2_formats_rgb, > + .num_formats = ARRAY_SIZE(wb2_formats_rgb), > + .clk_ctrl = DPU_CLK_CTRL_WB2, > + .xin_id = 6, > + .vbif_idx = VBIF_RT, > + .maxlinewidth = 2160, > + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), > + }, > +}; > + > static const struct dpu_intf_cfg sm6150_intf[] = { > { > .name = "intf_0", .id = INTF_0, > @@ -244,6 +260,8 @@ const struct dpu_mdss_cfg dpu_sm6150_cfg = { > .dspp = sm6150_dspp, > .pingpong_count = ARRAY_SIZE(sm6150_pp), > .pingpong = sm6150_pp, > + .wb_count = ARRAY_SIZE(sm6150_wb), > + .wb = sm6150_wb, > .intf_count = ARRAY_SIZE(sm6150_intf), > .intf = sm6150_intf, > .vbif_count = ARRAY_SIZE(sdm845_vbif), > > --- > base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2 > change-id: 20250106-add-writeback-support-for-sm6150-ba7657196ea8 > > Best regards,
On 2025/1/7 3:15, Abhinav Kumar wrote: > > > On 1/5/2025 10:39 PM, Fange Zhang wrote: >> On the SM6150 platform there is WB_2 block. Add it to the SM6150 catalog. >> >> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> >> --- >> A followup patch to add writeback configuration for the SM6150 catalog >> --- >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 18 ++++++++ >> ++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/ >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h >> index >> 621a2140f675fa28b3a7fcd8573e59b306cd6832..6d32deead77728264b6de6d5fd2843a81afdf355 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h >> @@ -27,6 +27,7 @@ static const struct dpu_mdp_cfg sm6150_mdp = { >> [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, >> [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, >> [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, >> + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, >> }, >> }; >> @@ -164,6 +165,21 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = { >> }, >> }; >> +static const struct dpu_wb_cfg sm6150_wb[] = { >> + { >> + .name = "wb_2", .id = WB_2, >> + .base = 0x66000, .len = 0x2c8, > > This is not correct. > > WB_2 offset is at 0x66000. However, MDP base address accounts for the > 0x1000 offset. So this should still be 0x65000. > > Why is 0x66000 used here? It does not match the docs. sorry, missed it, yes it should be 0x65000, will fix it in next patch. > > How was this change verified? i checked drm state, and found the new writeback connector is loaded successfully. > >> + .features = WB_SM8250_MASK, >> + .format_list = wb2_formats_rgb, >> + .num_formats = ARRAY_SIZE(wb2_formats_rgb), >> + .clk_ctrl = DPU_CLK_CTRL_WB2, >> + .xin_id = 6, >> + .vbif_idx = VBIF_RT, >> + .maxlinewidth = 2160, >> + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), >> + }, >> +}; >> + >> static const struct dpu_intf_cfg sm6150_intf[] = { >> { >> .name = "intf_0", .id = INTF_0, >> @@ -244,6 +260,8 @@ const struct dpu_mdss_cfg dpu_sm6150_cfg = { >> .dspp = sm6150_dspp, >> .pingpong_count = ARRAY_SIZE(sm6150_pp), >> .pingpong = sm6150_pp, >> + .wb_count = ARRAY_SIZE(sm6150_wb), >> + .wb = sm6150_wb, >> .intf_count = ARRAY_SIZE(sm6150_intf), >> .intf = sm6150_intf, >> .vbif_count = ARRAY_SIZE(sdm845_vbif), >> >> --- >> base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2 >> change-id: 20250106-add-writeback-support-for-sm6150-ba7657196ea8 >> >> Best regards,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index 621a2140f675fa28b3a7fcd8573e59b306cd6832..6d32deead77728264b6de6d5fd2843a81afdf355 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -27,6 +27,7 @@ static const struct dpu_mdp_cfg sm6150_mdp = { [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, }, }; @@ -164,6 +165,21 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = { }, }; +static const struct dpu_wb_cfg sm6150_wb[] = { + { + .name = "wb_2", .id = WB_2, + .base = 0x66000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats_rgb, + .num_formats = ARRAY_SIZE(wb2_formats_rgb), + .clk_ctrl = DPU_CLK_CTRL_WB2, + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 2160, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + static const struct dpu_intf_cfg sm6150_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -244,6 +260,8 @@ const struct dpu_mdss_cfg dpu_sm6150_cfg = { .dspp = sm6150_dspp, .pingpong_count = ARRAY_SIZE(sm6150_pp), .pingpong = sm6150_pp, + .wb_count = ARRAY_SIZE(sm6150_wb), + .wb = sm6150_wb, .intf_count = ARRAY_SIZE(sm6150_intf), .intf = sm6150_intf, .vbif_count = ARRAY_SIZE(sdm845_vbif),
On the SM6150 platform there is WB_2 block. Add it to the SM6150 catalog. Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> --- A followup patch to add writeback configuration for the SM6150 catalog --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) --- base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2 change-id: 20250106-add-writeback-support-for-sm6150-ba7657196ea8 Best regards,