| Message ID | 20250109-x1e-speedbin-b4-v1-2-009e812b7f2a@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show
Return-Path: <dri-devel-bounces@lists.freedesktop.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9BCFE77199 for <dri-devel@archiver.kernel.org>; Wed, 8 Jan 2025 22:43:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CA4C10ECA0; Wed, 8 Jan 2025 22:43:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.b="k4BK9X8m"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7466110EC9E; Wed, 8 Jan 2025 22:43:15 +0000 (UTC) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 508Ih0L4008331; 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Wed, 8 Jan 2025 22:43:10 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 14:43:05 -0800 From: Akhil P Oommen <quic_akhilpo@quicinc.com> Date: Thu, 9 Jan 2025 04:12:39 +0530 Subject: [PATCH RFC 2/4] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250109-x1e-speedbin-b4-v1-2-009e812b7f2a@quicinc.com> References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> In-Reply-To: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, "Konrad Dybcio" <konradybcio@kernel.org>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Marijn Suijten <marijn.suijten@somainline.org>, David Airlie <airlied@gmail.com>, "Simona Vetter" <simona@ffwll.ch>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Srinivas Kandagatla <srinivas.kandagatla@linaro.org> CC: <linux-arm-msm@vger.kernel.org>, <dri-devel@lists.freedesktop.org>, <freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, Akhil P Oommen <quic_akhilpo@quicinc.com> X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Support for Adreno X1-85 Speedbin along with new OPP levels
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diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index df599bf462207267a412eac8e01634189a696a59..5bc4735fb3e6e06ec62a352e2d40503b01084fd8 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -240,6 +240,7 @@ #define RPMH_REGULATOR_LEVEL_TURBO_L2 432 #define RPMH_REGULATOR_LEVEL_TURBO_L3 448 #define RPMH_REGULATOR_LEVEL_TURBO_L4 452 +#define RPMH_REGULATOR_LEVEL_TURBO_L5 456 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480
Update the RPMH level definitions to include TURBO_L5 corner. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> --- include/dt-bindings/power/qcom-rpmpd.h | 1 + 1 file changed, 1 insertion(+)