From patchwork Fri Jan 10 12:34:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UGF1bC1wbCBDaGVuICjpmbPmn4/pnJYp?= X-Patchwork-Id: 13935616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F010E77188 for ; Sat, 11 Jan 2025 00:10:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1778D10E542; Sat, 11 Jan 2025 00:10:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="qAIF2d1C"; dkim-atps=neutral Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1AE5610F0A9 for ; Fri, 10 Jan 2025 12:38:52 +0000 (UTC) X-UUID: d5be8e68cf4f11efbd192953cf12861f-20250110 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MGyQBUwYYEO4oshPjes0yXd0Yo2H13I9Vf3yrjfUpO4=; b=qAIF2d1CUJ8BZvpQ2xJov7yP5ov+1tsisqMuWq79Iz9tttdxK9iDGV3iog50PfPOjZ3eeTgybwQ3VyDpZJ2DCNJSsqvINJk5yUU5InMBYha5j9Wj5GXklz3+DrKDz45hUw7d9WIbVB3waY3g89Ra1ir4B7iBSNhbllsvl43rpTI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46, REQID:43bd1e08-2ef4-41d5-b1f7-96f43eb90ed4, IP:0, U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:60aa074, CLOUDID:b66f4e13-8831-4185-8e40-f83b1917e828, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 ,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: d5be8e68cf4f11efbd192953cf12861f-20250110 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 432231468; Fri, 10 Jan 2025 20:38:46 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 10 Jan 2025 20:38:46 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 10 Jan 2025 20:38:46 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 05/12] dt-bindings: display: mediatek: add OUTPROC yaml for MT8196 Date: Fri, 10 Jan 2025 20:34:01 +0800 Message-ID: <20250110123835.2719824-7-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250110123835.2719824-1-paul-pl.chen@mediatek.com> References: <20250110123835.2719824-1-paul-pl.chen@mediatek.com> MIME-Version: 1.0 X-Mailman-Approved-At: Sat, 11 Jan 2025 00:10:20 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: "Paul-pl.Chen" Add mediate,outproc.yaml to support OUTPROC for MT8196. Signed-off-by: Paul-pl.Chen --- The header used in examples: #include is not upstreamed yet. It will be sent by related owner soon. --- .../display/mediatek/mediatek,outproc.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml new file mode 100644 index 000000000000..b304ae41420f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap output processor + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC, + handles the post-stage of pixel processing in the overlapping procedure. + OVL_OUTPROC manages pixels for gamma correction and ensures that pixel + values are within the correct range. + +properties: + compatible: + const: mediatek,mt8196-outproc + + reg: + maxItems: 1 + + clocks: + items: + - description: Overlap Output Processor Clock + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + disp_ovl0_outproc0: outproc@32970000 { + compatible = "mediatek,mt8196-outproc"; + reg = <0 0x32970000 0 0x1000>; + clocks = <&ovlsys_config_clk CLK_OVL_OUTPROC0_DISP>; + interrupts = ; + }; + };