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Wed, 15 Jan 2025 23:26:16 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72d4059485bsm10164583b3a.83.2025.01.15.23.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 23:26:16 -0800 (PST) From: Jun Nie Date: Thu, 16 Jan 2025 15:25:51 +0800 Subject: [PATCH v4 02/16] drm/msm/dpu: Do not fix number of DSC MIME-Version: 1.0 Message-Id: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-2-74749c6eba33@linaro.org> References: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> In-Reply-To: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737012353; l=1814; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=u2GFE12qLfx13hrjSJDIvSRgATGg2YWsZ6oSOw/ZiU4=; b=B2zJX6OxJVLb1nrnneDJA+HhPR1wU8/wgPl7b3y+aZsPSv5T//cZ1Jt1PN18xaQ2mrJoaqZBN 5jJJG51NEgnAV9vF7u6k+bPJ9d7rg4hiMBWYlezra+R9lwvwAnGaIVL X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, if DSC is enabled, only 2 DSC engines are supported so far. More usage cases will be added, such as 4 DSC in 4:4:2 topology. So get the real number of DSCs to decide whether DSC merging is needed. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index eaac172141ede..c734d2c5790d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -164,6 +164,7 @@ enum dpu_enc_rc_states { * clks and resources after IDLE_TIMEOUT time. * @topology: topology of the display * @idle_timeout: idle timeout duration in milliseconds + * @num_dscs: Number of DSCs in use * @wide_bus_en: wide bus is enabled on this interface * @dsc: drm_dsc_config pointer, for DSC-enabled encoders */ @@ -204,6 +205,7 @@ struct dpu_encoder_virt { struct msm_display_topology topology; u32 idle_timeout; + u32 num_dscs; bool wide_bus_en; @@ -622,9 +624,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) if (dpu_enc->phys_encs[i]) intf_count++; - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ if (dpu_enc->dsc) - num_dsc = 2; + num_dsc = dpu_enc->num_dscs; return (num_dsc > 0) && (num_dsc > intf_count); } @@ -1261,6 +1262,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); } + dpu_enc->num_dscs = num_dsc; dpu_enc->dsc_mask = dsc_mask; if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||