From patchwork Tue Jan 21 06:23:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damon Ding X-Patchwork-Id: 13945688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10731C02187 for ; Tue, 21 Jan 2025 06:23:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 162FF10E4D5; Tue, 21 Jan 2025 06:23:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=rock-chips.com header.i=@rock-chips.com header.b="FkFHmyvd"; dkim-atps=neutral Received: from mail-m49200.qiye.163.com (mail-m49200.qiye.163.com [45.254.49.200]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFD6110E4D2 for ; Tue, 21 Jan 2025 06:23:47 +0000 (UTC) Received: from zyb-HP-ProDesk-680-G2-MT.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 9456a302; Tue, 21 Jan 2025 14:23:44 +0800 (GMT+08:00) From: Damon Ding To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rfoss@kernel.org, vkoul@kernel.org, sebastian.reichel@collabora.com, cristian.ciocaltea@collabora.com, l.stach@pengutronix.de, dmitry.baryshkov@linaro.org, andy.yan@rock-chips.com, hjc@rock-chips.com, algea.cao@rock-chips.com, kever.yang@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Damon Ding Subject: [PATCH v6 2/6] phy: phy-rockchip-samsung-hdptx: Supplement some register names with their full version Date: Tue, 21 Jan 2025 14:23:20 +0800 Message-Id: <20250121062324.309592-3-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250121062324.309592-1-damon.ding@rock-chips.com> References: <20250121062324.309592-1-damon.ding@rock-chips.com> MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRpNSFYYSUxLSUwdHUNKSEJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a948787fe0603a3kunm9456a302 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Kz46DTo5NTIQPDQIGRIrD0xJ GS0KCwNVSlVKTEhMT09LTUlNS0hOVTMWGhIXVR8aFhQVVR8SFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFKSU5KNwY+ DKIM-Signature: a=rsa-sha256; b=FkFHmyvdaS6TTl6rbJgujA3txHqy/pyV1jeixwGdnqKffV0zGdXpSwIA5cOQyM5xZ8J4hKB5rC3P6JiN+mdImCNjrsUsFUHMm+ohD/vrVFXzyDaUyKXPWLb1uzNebeGvbyToK/9vL5xZRwASP5veiyGfo/4aj90nB7Xw3xY0zy8=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=tywO7xGB2da8iEsHnvmYHdfB6wpe6ItXRYSerKfpSzc=; h=date:mime-version:subject:message-id:from; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their full version, and it can help to better match the datasheet. Signed-off-by: Damon Ding Reviewed-by: Dmitry Baryshkov --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index efbea5b67c89..423c61b7469f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -82,14 +82,14 @@ #define ROPLL_SSC_EN BIT(0) /* CMN_REG(0081) */ #define OVRD_PLL_CD_CLK_EN BIT(8) -#define PLL_CD_HSCLK_EAST_EN BIT(0) +#define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) /* CMN_REG(0086) */ #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) #define PLL_PCG_CLK_EN BIT(0) /* CMN_REG(0087) */ -#define PLL_FRL_MODE_EN BIT(3) -#define PLL_TX_HS_CLK_EN BIT(2) +#define ANA_PLL_FRL_MODE_EN BIT(3) +#define ANA_PLL_TX_HS_CLK_EN BIT(2) /* CMN_REG(0089) */ #define LCPLL_ALONE_MODE BIT(1) /* CMN_REG(0097) */