From patchwork Thu Jan 23 06:47:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Langyan Ye X-Patchwork-Id: 13947958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 210FDC02182 for ; Thu, 23 Jan 2025 06:48:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 903E010E6DA; Thu, 23 Jan 2025 06:48:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=huaqin-corp-partner-google-com.20230601.gappssmtp.com header.i=@huaqin-corp-partner-google-com.20230601.gappssmtp.com header.b="tggbEXrK"; dkim-atps=neutral Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by gabe.freedesktop.org (Postfix) with ESMTPS id 17D4310E6DA for ; Thu, 23 Jan 2025 06:48:18 +0000 (UTC) Received: by mail-pj1-f53.google.com with SMTP id 98e67ed59e1d1-2ee8e8e29f6so916870a91.0 for ; Wed, 22 Jan 2025 22:48:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20230601.gappssmtp.com; s=20230601; t=1737614897; x=1738219697; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VCOG5kt31moLV2eZoaA3/yFdIlV57mdvZJ7cZk6YoPg=; b=tggbEXrKYH4PZgmuXJWt23znERxVf/4aQXofzCVOmBbncPcW75y5BOzMjLZnxx8vgB kv49HRcuPGns1NasUWOz28ssRyjYZ0wz94uzGiK1tGUoFqXi3rMV7UGNUkcwkmmyZAmY Ti7OmEi+iYc4YqLsJpROGZgiTnxYvbQNapwW1yUbeH500QyRGj9qJU0YS4PD6bes6XXJ uIqwJ0DYatKKnwyH8ZNh5M7A1mxUy7QYiuejUT0I3rsuT3UV6Kquf885NHIBV5QNKWoY 1suf4YfrixFzbNzVmjmBHG04xCXw+WZCXU0lWEIgcQejUkmPTXTSBPOOHkM3337AXH6L Krsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737614897; x=1738219697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VCOG5kt31moLV2eZoaA3/yFdIlV57mdvZJ7cZk6YoPg=; b=K0g9YGnpwHKIWCm3EoDehVW1A9wkCvR4vS5Lv54MaEplCQ6n5LDMpgltPxaYMjYmFh cHIlS2dkib+COp2oO+kqPorve5rnQRUMHNqKWy2ra5RGnyMr5B3vt80wuo74neMtOeUo i6Gg9AmVgYBUCObNC+1nmH/SE7PCcX2K7KWDnb8dUfUUPwzXyeIF1yrDBB1C4w1slsH6 +HC/5qzqFiOtMdd1g+pq/MXcGvj6Fmb8+/owRjs04zVR3JpiYWGDVcQB7kkuw8wbZiTG 3ixx1Dpk6mpkt5suk/7LlQuAXdhAb0xaXM4lPYtNyYXsxKjrkR7po+1q+304W0F0JRAr zrvw== X-Gm-Message-State: AOJu0YzUrBozLmN+INODlokEodPxxTP2uV3GXZUusbAjR/S5cZ6Is+f3 ODTVvRSazqQOpe+TXPs0JkKf0ihfVmRHSRaIOZx03SPQmYYDPqhEwyXKzsky8dg= X-Gm-Gg: ASbGncsvXTrAsZMcWk5iP6qZ7WKNtzirAK8Rj717nUxKTXyyO+pf0fvXwpvSz98IEOp MxZHTnOc06OoblGGfBfPhSSDUhewOpLXDbFKsGIUEvt30zkxmV8LImWRKFD7CyGF0WQBRbQw/dS rAi6m+KMU1YUeoY6T1VAz8BXpyebbGvIcnJCreXjFGYiE6/m2QIeaWtEIPvsHaRqlFh2FbQ93ar znit/cZAba6KvQ9MSzPqdKCR/DiPUqrMldMkKNPwOU70KQpH5w3kp8KeGjVWnhIf+IrilIHWQWS wMfu7YkBMRChatrRHWiJVgQnB4JIkA8GbKut+8NQ+EPPe8Cjf39r X-Google-Smtp-Source: AGHT+IFSKRouPqtWjw8tzLodi2fOrUljW1EJSB7AMzNCQQ4bdGluCYsFI9JuIeJeA6yrQJivmxkPrQ== X-Received: by 2002:a17:90b:520d:b0:2ee:8e75:4ae1 with SMTP id 98e67ed59e1d1-2f782cbfcadmr32849393a91.21.1737614897542; Wed, 22 Jan 2025 22:48:17 -0800 (PST) Received: from dgp100339560-01.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-a9bcc323777sm11923454a12.20.2025.01.22.22.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 22:48:17 -0800 (PST) From: Langyan Ye To: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, sam@ravnborg.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Langyan Ye Subject: [PATCH v4 2/3] drm/panel: boe-tv101wum-nl6: support for kingdisplay-kd110n11-51ie MIPI-DSI panel Date: Thu, 23 Jan 2025 14:47:57 +0800 Message-Id: <20250123064758.743798-3-yelangyan@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> References: <20250123064758.743798-1-yelangyan@huaqin.corp-partner.google.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The kingdisplay-kd110n11-51ie is a 10.95" TFT panel. which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. From the datasheet, MIPI needs to keep the LP11 state before the lcm_reset pin is pulled high, so increase lp11_before_reset flag. Signed-off-by: Langyan Ye Reviewed-by: Neil Armstrong --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index 3e5b0d8636d0..2a84ce3a33ed 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1205,6 +1205,97 @@ static int auo_b101uan08_3_init(struct boe_panel *boe) return 0; }; +static int kingdisplay_kd110n11_51ie_init(struct boe_panel *boe) +{ + struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; + + msleep(50); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB9, 0x83, 0x10, 0x21, 0x55, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC4); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD9, 0xD1); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x2C, 0xB3, 0xB3, 0x31, 0xF1, 0x33, 0xE0, 0x54, + 0x36, 0x36, 0x3A, 0x3A, 0x32, 0x8B, 0x11, 0xE5, 0x98); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xD9); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x8B, 0x33); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x2C, 0x80, 0x3C, + 0x9F, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB4, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x40, 0x84, + 0x64, 0x84, 0x01, 0x9D, 0x01, 0x02, 0x01, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBC, 0x1B, 0x04); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBE, 0x20); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBF, 0xFC, 0xC4, 0x80, 0x9C, 0x36, 0x00, 0x0D, 0x04); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC0, 0x32, 0x32, 0x22, 0x11, 0x22, 0xA0, 0x31, 0x08, + 0xF5, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xCC); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC7, 0x80); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC6); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC8, 0x97); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x36); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCC, 0x02, 0x03, 0x44); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD1, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2C, 0xFF); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, 0x08, 0x04, + 0x08, 0x37, 0x07, 0x44, 0x37, 0x2B, 0x2B, 0x03, 0x03, 0x32, + 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, 0x29, 0x32, + 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, + 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x18, 0x18, + 0x25, 0x24, 0x25, 0x24, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, + 0x1E, 0x1E, 0x20, 0x20, 0x20, 0x20); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0, 0x0A, 0x2A, + 0xAA, 0x8A, 0xAA, 0xA0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0xE0, 0x10, 0x10, 0x0D, 0x1E, 0x9D, 0x02, 0x52, + 0x9D, 0x14, 0x14); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x01); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB1, 0x01, 0x7F, 0x11, 0xFD); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC5); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBA, 0x4F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x86); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD2, 0x64); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC5); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD3, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0, 0x0A, 0x2A, + 0xAA, 0x8A, 0xAA, 0xA0, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50, + 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0x02, 0x00, 0x24, 0x01, 0x7E, 0x0F, 0x7C, 0x10, + 0xA0, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x02); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xCB, 0x03, 0x07, 0x00, 0x10, 0x7B); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0F, 0x3F, 0xFF, 0xCF, 0xFF, 0xF0, 0x0F, 0x3F, + 0xFF, 0xCF, 0xFF, 0xF0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE7, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0x00, 0x00, + 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9D, + 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB2, 0x66, 0x81); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0xC6); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB4, 0x03, 0xFF, 0xF8); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xE9, 0x3F); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xD8, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0, 0x0A, 0x2A, + 0xAA, 0x8A, 0xAA, 0xA0, 0x0F, 0x2A, 0xAA, 0x8A, 0xAA, 0xF0, + 0x0F, 0x2A, 0xAA, 0x8A, 0xAA, 0xF0, 0x0A, 0x2A, 0xAA, 0x8A, + 0xAA, 0xA0, 0x0A, 0x2A, 0xAA, 0x8A, 0xAA, 0xA0); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xBD, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xB9, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); + + mipi_dsi_msleep(&ctx, 120); + + mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); + + mipi_dsi_msleep(&ctx, 20); + + return 0; +} + static int starry_qfh032011_53g_init(struct boe_panel *boe) { struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; @@ -1615,6 +1706,34 @@ static const struct panel_desc boe_tv105wum_nw0_desc = { .lp11_before_reset = true, }; +static const struct drm_display_mode kingdisplay_kd110n11_51ie_default_mode = { + .clock = 182888, + .hdisplay = 1200, + .hsync_start = 1200 + 124, + .hsync_end = 1200 + 124 + 80, + .htotal = 1200 + 124 + 80 + 80, + .vdisplay = 1920, + .vsync_start = 1920 + 88, + .vsync_end = 1920 + 88 + 8, + .vtotal = 1920 + 88 + 8 + 38, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc kingdisplay_kd110n11_51ie_desc = { + .modes = &kingdisplay_kd110n11_51ie_default_mode, + .bpc = 8, + .size = { + .width_mm = 147, + .height_mm = 235, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init = kingdisplay_kd110n11_51ie_init, + .lp11_before_reset = true, +}; + static const struct drm_display_mode starry_qfh032011_53g_default_mode = { .clock = 165731, .hdisplay = 1200, @@ -1804,6 +1923,9 @@ static const struct of_device_id boe_of_match[] = { { .compatible = "innolux,hj110iz-01a", .data = &inx_hj110iz_desc }, + { .compatible = "kingdisplay,kd110n11-51ie", + .data = &kingdisplay_kd110n11_51ie_desc + }, { .compatible = "starry,2081101qfh032011-53g", .data = &starry_qfh032011_53g_desc },