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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 9818aeaa; Thu, 23 Jan 2025 18:08:26 +0800 (GMT+08:00) From: Damon Ding To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rfoss@kernel.org, vkoul@kernel.org, sebastian.reichel@collabora.com, cristian.ciocaltea@collabora.com, l.stach@pengutronix.de, dmitry.baryshkov@linaro.org, andy.yan@rock-chips.com, hjc@rock-chips.com, algea.cao@rock-chips.com, kever.yang@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Damon Ding Subject: [PATCH v6 14/14] arm64: dts: rockchip: Enable eDP0 display on RK3588S EVB1 board Date: Thu, 23 Jan 2025 18:07:47 +0800 Message-Id: <20250123100747.1841357-15-damon.ding@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123100747.1841357-1-damon.ding@rock-chips.com> References: <20250123100747.1841357-1-damon.ding@rock-chips.com> MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUhDTVYfGhpJSEkaQ0hKGBhWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a9492a26dc903a3kunm9818aeaa X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Kxg6CSo4DjIXAiwhQy8MFC4a PglPChpVSlVKTEhMTUlNQktMQ01NVTMWGhIXVR8aFhQVVR8SFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFIS09MNwY+ DKIM-Signature: a=rsa-sha256; b=c5oMEw37dqbnJD8ktSkVn9RySXg6eGPCsZZSCalKue5jcAkthX/LUhz/Pf9pO0Bq1e4ywwfspJakhn8U6aUgWHb7x+hHnlbv5BM5bx0VM7Rvu9AZT3yE2lyFRDk0jELTsugIraBCepNgJvtivXh2sjVH86sz9SJiqA8ajC921f4=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=w2jc5EE3lG/zMJ1adKGUc5gwTeRb2bBedZedT78sPY0=; h=date:mime-version:subject:message-id:from; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the necessary DT changes to enable eDP0 on RK3588S EVB1 board: - Set pinctrl of pwm12 for backlight - Enable edp0/hdptxphy0/vp2 - Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL - Add aux-bus/panel nodes For RK3588, the PLL_V0PLL is specifically designed for the VOP2. This means the clock rate of PLL_V0PLL can be adjusted according to the dclk rate of relevant VP. It is typically assigned as the dclk source of a specific VP when the clock of relevant display mode is unusual, such as the eDP panel 'lg,lp079qx1-sp0v' paired with RK3588S EVB1, which has a clock rate of 202.02MHz. Signed-off-by: Damon Ding --- Changes in v2: - Remove brightness-levels and default-brightness-level properties in backlight node. - Add the detail DT changes to commit message. Changes in v3: - Use aux-bus instead of platform bus for edp-panel. Changes in v4: - Add comments related to the use of panel compatible "lg,lp079qx1-sp0v" in the commit message. Changes in v5: - Use "edp-panel" instead of "lg,lp079qx1-sp0v" - Remove unnecessary comments in commit message - Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL Changes in v6: - Add PLL_V0PLL related descriptions in commit message --- .../boot/dts/rockchip/rk3588s-evb1-v10.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts index bc4077575beb..a8c151b41e21 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "rk3588s.dtsi" @@ -238,6 +239,41 @@ &combphy2_psu { status = "okay"; }; +&edp0 { + force-hpd; + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp0_in { + edp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_edp0>; + }; +}; + +&edp0_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c3 { status = "okay"; @@ -399,6 +435,7 @@ usbc0_int: usbc0-int { }; &pwm12 { + pinctrl-0 = <&pwm12m1_pins>; status = "okay"; }; @@ -1168,3 +1205,20 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 { }; }; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; + status = "okay"; +}; + +&vp2 { + vp2_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 { + reg = ; + remote-endpoint = <&edp0_in_vp2>; + }; +};