| Message ID | 20250131-drm-msm-phy-pll-cfg-reg-v1-3-3b99efeb2e8d@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dsi/phy: Improvements around concurrent PHY_CMN_CLK_CFG[01] | expand |
On Fri, Jan 31, 2025 at 04:02:52PM +0100, Krzysztof Kozlowski wrote: > PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI > clock divider, source of bitclk and two for enabling the DSI PHY PLL > clocks. > > dsi_7nm_set_usecase() sets only the source of bitclk, so should leave > all other bits untouched. Use newly introduced > dsi_pll_cmn_clk_cfg1_update() to update respective bits without > overwriting the rest. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 6c18b9c0e1903bbd0090aceef13ae8c6f2e080ce..8a9ee308ccffc3b9d112a994a064d8be06d9c42e 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -615,7 +615,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) > static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) > { > struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); > - void __iomem *base = phy->base; > u32 data = 0x0; /* internal PLL */ > > DBG("DSI PLL%d", pll_7nm->phy->id); > @@ -634,7 +633,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) > } > > /* set PLL src */ > - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); > + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); This also should be defined. > > return 0; > } > > -- > 2.43.0 >
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 6c18b9c0e1903bbd0090aceef13ae8c6f2e080ce..8a9ee308ccffc3b9d112a994a064d8be06d9c42e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -615,7 +615,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); - void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_7nm->phy->id); @@ -634,7 +633,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2); return 0; }
PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI clock divider, source of bitclk and two for enabling the DSI PHY PLL clocks. dsi_7nm_set_usecase() sets only the source of bitclk, so should leave all other bits untouched. Use newly introduced dsi_pll_cmn_clk_cfg1_update() to update respective bits without overwriting the rest. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)