From patchwork Tue Feb 4 12:40:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13959084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0975CC02198 for ; Tue, 4 Feb 2025 12:40:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C60910E60D; Tue, 4 Feb 2025 12:40:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="KWUz5lep"; dkim-atps=neutral Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id 023B910E606 for ; Tue, 4 Feb 2025 12:40:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1738672817; bh=3J9xxfQwD8O+MObCBKMhxdwcXLG6TsI/zNsabrCHt74=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KWUz5lep24R+x82pNGmkKte6dB2oHv7l/Htv0qQLrXRAJDMu2UaZj9upKko2HWPuB 7JRkkVuf/Y/lM9At+n7nDvJh4ur3Fwlt1t4EXn2uMHsHg9LaJaMS4KpFXcsrzbaVCx poraT2lYXK1hf/LDkQtKjy6dH3bCauCJ1ceMS4Ff4JB9oFt7JW5X31pZG4amygXokO UOSJ9deUoHZ4SwZtobEopdyLW+8xAj1dhWZg/C90KTYd7jhsBldphLYBoOACTwOe0F ZE7omuLf3VD2jcbnL0e0lr8KQnHbwNYUmm1gHJk1bbr6MX5ghCltCS+yYnTmKafNAy ALRZwl7NRVotQ== Received: from localhost (unknown [188.27.43.189]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 84A8417E151F; Tue, 4 Feb 2025 13:40:17 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Feb 2025 14:40:07 +0200 Subject: [PATCH v3 4/5] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 MIME-Version: 1.0 Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com> References: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58@collabora.com> In-Reply-To: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI0 PHY. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 8cfa30837ce72581d0b513a8274ab0177eb5ae15..c2d1f08e55d4cb4b4d2b6a89f26542fdc99fd604 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2812,6 +2812,7 @@ hdptxphy_hdmi0: phy@fed60000 { reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,