From patchwork Wed Feb 12 09:44:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13971637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 759CFC02198 for ; Wed, 12 Feb 2025 09:53:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCA9610E1DC; Wed, 12 Feb 2025 09:53:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="Zo3lHM3h"; dkim-atps=neutral X-Greylist: delayed 426 seconds by postgrey-1.36 at gabe; Wed, 12 Feb 2025 09:53:02 UTC Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C4B810E1DC for ; Wed, 12 Feb 2025 09:53:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739353983; x=1770889983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vnx2AdOW50HMFVLSHH43ey2HhNMvsX6+y6C07WIJ1a8=; b=Zo3lHM3hvo0y6a0D8jhR5j23hyJJvIj8dXbGeqGFtNg4n3RJbsmPTtzB 1V2CNKNkjG3Ec582zPKB/SdZhSQVLkCvgKxXfxt6Rq+Bzpzm/xJ4p+hAv pA/Y8YFTE2IAUiKTe/YYxCSXrRuGSZwvK838bQHCEF7uPoK9jBwh3HteM kfBegFOB8vDJvJW3xGNvepKDNjn8M2NorvYNuOtqQeWNT/5sy//WMelnx caUEV+nj+HxhNYeFkam1YzVSznMU4xt//DGFHXdeRYoylCHUdZZFybQHs uQBs6ANf+FvMLEm6WioJ8KNYYl9sKqcJraxWHiMYMq1yQ/ToF5fRCA1qm Q==; X-CSE-ConnectionGUID: 8MuVtLdRQ2uCYR3xxsN4MA== X-CSE-MsgGUID: poXRycaeTVyvkAHRJFv8uw== X-IronPort-AV: E=Sophos;i="6.13,279,1732604400"; d="scan'208";a="37585559" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Feb 2025 02:45:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 12 Feb 2025 02:45:14 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 12 Feb 2025 02:45:08 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , CC: Dharma Balasubiramani , Manikandan Muralidharan Subject: [PATCH v2 3/3] drm: atmel-hlcdc: set LVDS PLL clock rate for LVDS Displays Date: Wed, 12 Feb 2025 15:14:49 +0530 Message-ID: <20250212094449.109622-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250212094449.109622-1-manikandan.m@microchip.com> References: <20250212094449.109622-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Dharma Balasubiramani The LVDS PLL clock runs at 7 times the panel pixel clock. For LVDS displays, the PLL clock rate is set based on the panel pixel clock, eliminating the need for the assigned-clock-rates Device Tree property for lvds_pll_clk in the LCD node. Signed-off-by: Dharma Balasubiramani Signed-off-by: Manikandan Muralidharan --- Changes in v2: - Rephrase commit message and comment block --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 48 ++++++++++++++++--- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 0e709047369a..cf4f9ccd81a4 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -99,9 +99,15 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) drm_connector_list_iter_end(&iter); } - ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); - if (ret) - return; + if (crtc->dc->hlcdc->lvds_pll_clk) { + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + if (ret) + return; + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (ret) + return; + } vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; @@ -186,7 +192,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); } static enum drm_mode_status @@ -242,7 +251,11 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, 10, 1000)) dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n"); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + pinctrl_pm_select_sleep_state(dev->dev); pm_runtime_allow(dev->dev); @@ -255,15 +268,38 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct drm_display_mode *adj = &c->state->adjusted_mode; struct regmap *regmap = crtc->dc->hlcdc->regmap; unsigned int status; + int ret; pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); pinctrl_pm_select_default_state(dev->dev); - clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + + if (crtc->dc->hlcdc->lvds_pll_clk) { + /* + * For LVDS displays, retrieve the pixel clock from the panel + * and set the LVDS PLL clock rate accordingly. + * According to the datasheet,the LVDS PLL clock is 7 times the pixel clock. + */ + ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk, + (adj->clock * 7 * 1000)); + if (ret) { + dev_err(dev->dev, "Failed to set LVDS PLL clk rate: %d\n", ret); + return; + } + + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + if (ret) + return; + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (ret) + return; + } regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,