| Message ID | 20250214-drm-msm-phy-pll-cfg-reg-v3-3-0943b850722c@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm/dsi/phy: Improvements around concurrent PHY_CMN_CLK_CFG[01] | expand |
On Fri, Feb 14, 2025 at 04:08:43PM +0100, Krzysztof Kozlowski wrote: > PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI > clock divider, source of bitclk and two for enabling the DSI PHY PLL > clocks. > > dsi_7nm_set_usecase() sets only the source of bitclk, so should leave > all other bits untouched. Use newly introduced > dsi_pll_cmn_clk_cfg1_update() to update respective bits without > overwriting the rest. > > While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to > make the code more readable and obvious. > > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Changes in v3: > 1. Define bitfields (move here parts from patch #4) > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++-- > drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 + > 2 files changed, 3 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 2/14/2025 7:08 AM, Krzysztof Kozlowski wrote: > PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI > clock divider, source of bitclk and two for enabling the DSI PHY PLL > clocks. > > dsi_7nm_set_usecase() sets only the source of bitclk, so should leave > all other bits untouched. Use newly introduced > dsi_pll_cmn_clk_cfg1_update() to update respective bits without > overwriting the rest. > > While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to > make the code more readable and obvious. > > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Changes in v3: > 1. Define bitfields (move here parts from patch #4) > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++-- > drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 + > 2 files changed, 3 insertions(+), 2 deletions(-) > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 388017db45d802c4ef1299296f932c4182512aae..798168180c1ab6c96ec2384f854302720cb27932 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -617,7 +617,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); - void __iomem *base = phy->base; u32 data = 0x0; /* internal PLL */ DBG("DSI PLL%d", pll_7nm->phy->id); @@ -636,7 +635,8 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - writel(data << 2, base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__MASK, + DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL(data)); return 0; } diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index cfaf78c028b1325682889a5c2d8fffd0268122cf..35f7f40e405b7dd9687725eae754522a7136725e 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -16,6 +16,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0x00014" name="CLK_CFG1"> <bitfield name="CLK_EN" pos="5" type="boolean"/> <bitfield name="CLK_EN_SEL" pos="4" type="boolean"/> + <bitfield name="BITCLK_SEL" low="2" high="3" type="uint"/> </reg32> <reg32 offset="0x00018" name="GLBL_CTRL"/> <reg32 offset="0x0001c" name="RBUF_CTRL"/>
PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI clock divider, source of bitclk and two for enabling the DSI PHY PLL clocks. dsi_7nm_set_usecase() sets only the source of bitclk, so should leave all other bits untouched. Use newly introduced dsi_pll_cmn_clk_cfg1_update() to update respective bits without overwriting the rest. While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes in v3: 1. Define bitfields (move here parts from patch #4) --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++-- drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 + 2 files changed, 3 insertions(+), 2 deletions(-)