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Mon, 17 Feb 2025 14:05:01 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::6e37:569f:82ee:3f99]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::6e37:569f:82ee:3f99%6]) with mapi id 15.20.8445.017; Mon, 17 Feb 2025 14:05:01 +0000 From: Alexandre Courbot Date: Mon, 17 Feb 2025 23:04:48 +0900 Subject: [PATCH RFC 3/3] gpu: nova-core: add basic timer device Message-Id: <20250217-nova_timer-v1-3-78c5ace2d987@nvidia.com> References: <20250217-nova_timer-v1-0-78c5ace2d987@nvidia.com> In-Reply-To: <20250217-nova_timer-v1-0-78c5ace2d987@nvidia.com> To: Danilo Krummrich , David Airlie , John Hubbard , Ben Skeggs Cc: linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Alexandre Courbot X-Mailer: b4 0.14.2 X-ClientProxiedBy: TYAPR01CA0079.jpnprd01.prod.outlook.com (2603:1096:404:2c::19) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|MN2PR12MB4208:EE_ X-MS-Office365-Filtering-Correlation-Id: c2b42191-45a7-45f9-c0ba-08dd4f5c11d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This first draft is probably very questionable. One point in particular which should IMHO receive attention: the generic wait_on() method aims at providing similar functionality to Nouveau's nvkm_[num]sec() macros. Since this method will be heavily used with different conditions to test, I'd like to avoid monomorphizing it entirely with each instance ; that's something that is achieved in nvkm_xsec() using functions that the macros invoke. I have tried achieving the same result in Rust using closures (kept as-is in the current code), but they seem to be monomorphized as well. Calling extra functions could work better, but looks also less elegant to me, so I am really open to suggestions here. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 4 +- drivers/gpu/nova-core/gpu.rs | 35 ++++++++++++++- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 43 ++++++++++++++++++ drivers/gpu/nova-core/timer.rs | 91 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 172 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver.rs index 63c19f140fbdd65d8fccf81669ac590807cc120f..0cd23aa306e4082405f480afc0530a41131485e7 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -10,7 +10,7 @@ pub(crate) struct NovaCore { pub(crate) gpu: Gpu, } -const BAR0_SIZE: usize = 8; +const BAR0_SIZE: usize = 0x9500; pub(crate) type Bar0 = pci::Bar; kernel::pci_device_table!( @@ -42,6 +42,8 @@ fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) -> Result> GFP_KERNEL, )?; + let _ = this.gpu.test_timer(); + Ok(this) } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index e7da6a2fa29d82e9624ba8baa2c7281f38cb3133..2fbf4041f6d421583636c7bede449c3416272301 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -1,12 +1,16 @@ // SPDX-License-Identifier: GPL-2.0 +use kernel::device::Device; +use kernel::types::ARef; use kernel::{ device, devres::Devres, error::code::*, firmware, fmt, pci, prelude::*, str::CString, }; use crate::driver::Bar0; use crate::regs; +use crate::timer::Timer; use core::fmt; +use core::time::Duration; /// Enum representation of the GPU chipset. #[derive(fmt::Debug)] @@ -165,10 +169,12 @@ fn new(dev: &device::Device, spec: &Spec, ver: &str) -> Result { /// Structure holding the resources required to operate the GPU. #[pin_data] pub(crate) struct Gpu { + dev: ARef, spec: Spec, /// MMIO mapping of PCI BAR 0 bar: Devres, fw: Firmware, + timer: Timer, } impl Gpu { @@ -184,6 +190,33 @@ pub(crate) fn new(pdev: &pci::Device, bar: Devres) -> Result Result<()> { + let bar = self.bar.try_access().ok_or(ENXIO)?; + + dev_info!(&self.dev, "testing timer subdev\n"); + assert!(matches!( + self.timer + .wait_on(&bar, Duration::from_millis(10), || Some(())), + Ok(()) + )); + assert_eq!( + self.timer + .wait_on(&bar, Duration::from_millis(10), || Option::<()>::None), + Err(ETIMEDOUT) + ); + + Ok(()) } } diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nova_core.rs index 5d0230042793dae97026146e94f3cdb31ba20642..94b165a340ddfffd448f87cd82200391de075806 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -5,6 +5,7 @@ mod driver; mod gpu; mod regs; +mod timer; kernel::module_pci_driver! { type: driver::NovaCore, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index f2766f95e9d1eeab6734b18525fe504e1e7ea587..5127cc3454c047d64b7aaf599d8bf5f63a08bdfe 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -54,3 +54,46 @@ pub(crate) fn major_rev(&self) -> u8 { ((self.0 & BOOT0_MAJOR_REV_MASK) >> BOOT0_MAJOR_REV_SHIFT) as u8 } } + +const PTIMER_TIME_0: usize = 0x00009400; +const PTIMER_TIME_1: usize = 0x00009410; + +#[derive(Copy, Clone, PartialEq, Eq)] +pub(crate) struct PtimerTime0(u32); + +impl PtimerTime0 { + #[inline] + pub(crate) fn read(bar: &Bar0) -> Self { + Self(bar.readl(PTIMER_TIME_0)) + } + + #[inline] + pub(crate) fn write(bar: &Bar0, val: u32) { + bar.writel(val, PTIMER_TIME_0) + } + + #[inline] + pub(crate) fn lo(&self) -> u32 { + self.0 + } +} + +#[derive(Copy, Clone, PartialEq, Eq)] +pub(crate) struct PtimerTime1(u32); + +impl PtimerTime1 { + #[inline] + pub(crate) fn read(bar: &Bar0) -> Self { + Self(bar.readl(PTIMER_TIME_1)) + } + + #[inline] + pub(crate) fn write(bar: &Bar0, val: u32) { + bar.writel(val, PTIMER_TIME_1) + } + + #[inline] + pub(crate) fn hi(&self) -> u32 { + self.0 + } +} diff --git a/drivers/gpu/nova-core/timer.rs b/drivers/gpu/nova-core/timer.rs new file mode 100644 index 0000000000000000000000000000000000000000..f6a787d4fbdb90b3dc13e322d50da1c7f64818df --- /dev/null +++ b/drivers/gpu/nova-core/timer.rs @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Nova Core Timer subdevice + +use core::time::Duration; + +use kernel::num::U64Ext; +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::regs; + +pub(crate) struct Timer {} + +impl Timer { + pub(crate) fn new() -> Self { + Self {} + } + + pub(crate) fn read(bar: &Bar0) -> u64 { + loop { + let hi = regs::PtimerTime1::read(bar); + let lo = regs::PtimerTime0::read(bar); + + if hi == regs::PtimerTime1::read(bar) { + return u64::from_u32s(hi.hi(), lo.lo()); + } + } + } + + #[allow(dead_code)] + pub(crate) fn time(bar: &Bar0, time: u64) { + let (hi, lo) = time.into_u32s(); + + regs::PtimerTime1::write(bar, hi); + regs::PtimerTime0::write(bar, lo); + } + + /// Wait until `cond` is true or `timeout` elapsed, based on GPU time. + /// + /// When `cond` evaluates to `Some`, its return value is returned. + /// + /// `Err(ETIMEDOUT)` is returned if `timeout` has been reached without `cond` evaluating to + /// `Some`, or if the timer device is stuck for some reason. + pub(crate) fn wait_on Option>( + &self, + bar: &Bar0, + timeout: Duration, + cond: F, + ) -> Result { + // Number of consecutive time reads after which we consider the timer frozen if it hasn't + // moved forward. + const MAX_STALLED_READS: usize = 16; + + let (mut cur_time, mut prev_time, deadline) = (|| { + let cur_time = Timer::read(bar); + let deadline = + cur_time.saturating_add(u64::try_from(timeout.as_nanos()).unwrap_or(u64::MAX)); + + (cur_time, cur_time, deadline) + })(); + let mut num_reads = 0; + + loop { + if let Some(ret) = cond() { + return Ok(ret); + } + + (|| { + cur_time = Timer::read(bar); + + /* Check if the timer is frozen for some reason. */ + if cur_time == prev_time { + if num_reads >= MAX_STALLED_READS { + return Err(ETIMEDOUT); + } + num_reads += 1; + } else { + if cur_time >= deadline { + return Err(ETIMEDOUT); + } + + num_reads = 0; + prev_time = cur_time; + } + + Ok(()) + })()?; + } + } +}