From patchwork Thu Feb 20 10:41:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13983724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0092C021B3 for ; Thu, 20 Feb 2025 10:42:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D34D610E93B; Thu, 20 Feb 2025 10:42:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eiy/tyol"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B92C10E92E; Thu, 20 Feb 2025 10:42:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740048175; x=1771584175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xu44SbTAhg/5W4a9NTtP8h5OHBQNKTLaF9go05cb7co=; b=eiy/tyolnC7P1Ee2GyWKmQgV/G/L4MJ+a/mzL519vl1hhjyXrGwA4E2+ aYaKZe2cdltBL10cxHQd5EOUafXfkMPXvYSsehVp/vYwACKK5OtvWCzTJ p3jcSug74uNtVJn0xI5obxySY0OiBw1zaRl4ZVgFqFvKCmMaHFUOJKZNX ZDg9+0CyZgxriVtg4J+s0rpGqeVoK5RGDwLw0osTPY1SL/HEAotMA05ez svcY//IgupkZCusgbkdT60TYPQ03K3XO5p7blwkxOrpxHD7juZw5MN3pc Z1Vm34gfz2+S/eb5bLfvkfyYv6QzS9UFUS2oc4cTc+JXN+7kpe7pTEaXs Q==; X-CSE-ConnectionGUID: puXyCbEwSGa7J039k3lFIQ== X-CSE-MsgGUID: SGCyWTWUSx6Nn4KptEXC5A== X-IronPort-AV: E=McAfee;i="6700,10204,11350"; a="51804890" X-IronPort-AV: E=Sophos;i="6.13,301,1732608000"; d="scan'208";a="51804890" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 02:42:55 -0800 X-CSE-ConnectionGUID: eTQCZoCpRri44ESW6CV/kA== X-CSE-MsgGUID: 4aPHBpblQfek2qccYU+wTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,301,1732608000"; d="scan'208";a="119941969" Received: from slindbla-desk.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.224]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2025 02:42:51 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, vinod.govindapillai@intel.com, ville.syrjala@linux.intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v9 7/8] drm/i915/fbc: disable FBC if PSR2 selective fetch is enabled Date: Thu, 20 Feb 2025 12:41:43 +0200 Message-ID: <20250220104144.207526-8-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250220104144.207526-1-vinod.govindapillai@intel.com> References: <20250220104144.207526-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It is not recommended to have both FBC dirty rect and PSR2 selective fetch be enabled at the same time. Mark FBC as not possible, if PSR2 selective fetch is enabled. v2: fix the condition to disable FBC if PSR2 enabled (Jani) v3: use HAS_FBC_DIRTY_RECT() v4: Update to patch description Bspec: 68881 Reviewed-by: Ville Syrjälä Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 01d4540424b5..6222eea4b1ce 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1433,9 +1433,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; }