From patchwork Fri Mar 21 09:33:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "paul-pl.chen" X-Patchwork-Id: 14025092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B774C36002 for ; Fri, 21 Mar 2025 09:35:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B6B310E0C5; Fri, 21 Mar 2025 09:35:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="DjpdAuva"; dkim-atps=neutral Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id D0DEC10E0C5 for ; Fri, 21 Mar 2025 09:35:05 +0000 (UTC) X-UUID: c18ec0d8063711f08eb9c36241bbb6fb-20250321 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=j3XZVVX4nT3Yo0YKOnG/wibSc0FBMXKfOMnK+MEXxsk=; b=DjpdAuvaGb/RTSbNifjPUm2gLUeKSM6WlPCVHF5oKC4k+Fq1VQnhwI4cVtg/Po50zRenINP18Ufk6aW8P9LeET328jKKCY6G84z8VKuEIcyrZ03U0ue+OZ8RO2EMKtINUnaQD9r/0/WAevYqid02dTZtswvCRL4ZpnggPQTiXH4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:0b4c36a7-d81f-4e9e-9966-9511c612e558, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:5a79a1c6-16da-468a-87f7-8ca8d6b3b9f7, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c18ec0d8063711f08eb9c36241bbb6fb-20250321 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 818943364; Fri, 21 Mar 2025 17:34:58 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 21 Mar 2025 17:34:57 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 21 Mar 2025 17:34:57 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 01/15] dt-bindings: arm: mediatek: mmsys: add compatible for MT8196 Date: Fri, 21 Mar 2025 17:33:30 +0800 Message-ID: <20250321093435.94835-2-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321093435.94835-1-paul-pl.chen@mediatek.com> References: <20250321093435.94835-1-paul-pl.chen@mediatek.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Paul-pl Chen In previous SoCs, a single HW pipeline was an independent mmsys, which included the OVL module, PQ module, and display interface module. In the 8196, to increase the flexibility of pipeline connection and control, the OVL module on a single HW pipeline was separated into two mmsys, namely ovlsys0 and ovlsys1. The PQ module was also separated into a dispsys0, and the display interface module was separated into a dispsys1. Additionally, display power-related settings are controlled through vdiso-ao. For example: The primary path and external path of the display both use ovlsys0 -> dispsys0 -> dispsys1, forming a pipeline. The third path of the display uses ovlsys1 -> dispsys0 -> dispsys1, forming another pipeline. Therefore, the 8196 needs to add 5 compatible string to support mmsys for MT8196. Signed-off-by: Paul-pl Chen Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 3f4262e93c78..5f244a8f6a47 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -39,6 +39,11 @@ properties: - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 - mediatek,mt8195-vppsys1 + - mediatek,mt8196-dispsys0 + - mediatek,mt8196-dispsys1 + - mediatek,mt8196-ovlsys0 + - mediatek,mt8196-ovlsys1 + - mediatek,mt8196-vdisp-ao - mediatek,mt8365-mmsys - const: syscon