| Message ID | 20250321093435.94835-6-paul-pl.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add MediaTek SoC DRM support for MT8196 | expand |
On Fri, Mar 21, 2025 at 05:33:34PM +0800, paul-pl.chen wrote: > From: Paul-pl Chen <paul-pl.chen@mediatek.com> > > Add mediate,outproc.yaml to support OUTPROC for MT8196. > MediaTek display overlap output processor, namely OVL_OUTPROC > or OUTPROC,handles the post-stage of pixel processing in the > overlapping procedure. > > Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com> > --- > .../display/mediatek/mediatek,outproc.yaml | 54 +++++++++++++++++++ > 1 file changed, 54 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml > new file mode 100644 > index 000000000000..f42e9abc1436 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek display overlap output processor > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Philipp Zabel <p.zabel@pengutronix.de> > + > +description: | Don't need '|' if no formatting to preserve. > + MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC, > + handles the post-stage of pixel processing in the overlapping procedure. > + OVL_OUTPROC manages pixels for gamma correction and ensures that pixel > + values are within the correct range. > + > +properties: > + compatible: > + const: mediatek,mt8196-outproc > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + disp_ovl0_outproc0: outproc@32970000 { Drop unused labels. > + compatible = "mediatek,mt8196-outproc"; > + reg = <0 0x32970000 0 0x1000>; > + clocks = <&ovlsys_config_clk 49>; > + interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH 0>; > + }; > + }; > -- > 2.45.2 >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml new file mode 100644 index 000000000000..f42e9abc1436 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap output processor + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + +description: | + MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC, + handles the post-stage of pixel processing in the overlapping procedure. + OVL_OUTPROC manages pixels for gamma correction and ensures that pixel + values are within the correct range. + +properties: + compatible: + const: mediatek,mt8196-outproc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + disp_ovl0_outproc0: outproc@32970000 { + compatible = "mediatek,mt8196-outproc"; + reg = <0 0x32970000 0 0x1000>; + clocks = <&ovlsys_config_clk 49>; + interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH 0>; + }; + };