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Tue, 08 Apr 2025 13:09:30 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:469:6216:b7f8:fc55]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1795782sm174892875e9.26.2025.04.08.13.09.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 13:09:29 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Tomi Valkeinen , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Tommaso Merciai , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v2 04/15] dt-bindings: display: bridge: renesas, dsi: Add support for RZ/V2H(P) SoC Date: Tue, 8 Apr 2025 21:09:01 +0100 Message-ID: <20250408200916.93793-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250408200916.93793-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250408200916.93793-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To accommodate these differences, a SoC-specific `renesas,r9a09g057-mipi-dsi` compatible string has been added for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski --- v1->v2: - Added enum for RZ/V2H as suggested by Krzysztof as the list will grow in the future (while adding RZ/G3E SoC). - Added Reviewed-by tag from Krzysztof. --- .../bindings/display/bridge/renesas,dsi.yaml | 116 +++++++++++++----- 1 file changed, 87 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index e08c24633926..5980df2b389b 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,17 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: + oneOf: - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) + + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi reg: maxItems: 1 @@ -49,34 +50,56 @@ properties: - const: debug clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst power-domains: maxItems: 1 @@ -130,6 +153,41 @@ required: additionalProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include