From patchwork Thu Apr 10 09:55:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Coster X-Patchwork-Id: 14046233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD73DC369A4 for ; Thu, 10 Apr 2025 09:56:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EF09D10E8F8; Thu, 10 Apr 2025 09:55:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=imgtec.com header.i=@imgtec.com header.b="BxbKICnJ"; dkim-atps=neutral Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) by gabe.freedesktop.org (Postfix) with ESMTPS id C730910E8E2 for ; Thu, 10 Apr 2025 09:55:43 +0000 (UTC) Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53A60F8T032471; Thu, 10 Apr 2025 10:55:26 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=A 6WfJkonovfkEunMBDXC+DViM4ryLZzQzXSCf5RpGlQ=; b=BxbKICnJYDa8uXGun iv+Hikwlk9A1hCiKKy8c2ddMmsTnU0Nb1yFr+FVGHhYR/pI4dOyApCUNOE6CfrTi EnBBX5LGdTH+ZI9X91LqIyGNOcDHj6IjTxPknVRL9X4naExWu7wsQYQdzzGaL5Yv RvIFZgOb6WFuplMt5w5ftP83k4jgpLDciHcZbhFsEMuZXQgnCL43YVo870ykpgn1 LZPwP/urasgrzOlgquf5OpQUS5IIAwWC7unny1YkWS4+Ib9WMp3fc9e7iJydgx3J eG7209ra6AJi/zpyrH2qQcw1trGU/Um98KVk4+BAZMCx9IAaJ7VNgzv2MYJdVpRw JwY1Q== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 45w86h1d34-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 10 Apr 2025 10:55:25 +0100 (BST) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.6.134) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Apr 2025 10:55:24 +0100 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:09 +0100 Subject: [PATCH v6 10/18] drm/imagination: Make has_fixed_data_addr a value MIME-Version: 1.0 Message-ID: <20250410-sets-bxs-4-64-patch-v1-v6-10-eda620c5865f@imgtec.com> References: <20250410-sets-bxs-4-64-patch-v1-v6-0-eda620c5865f@imgtec.com> In-Reply-To: <20250410-sets-bxs-4-64-patch-v1-v6-0-eda620c5865f@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Michal Wilczynski" , Alessio Belle , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5427; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=lVgoW/tYLbUSJeSjrZM2ND1gf7iusYbgwUXx0Gibi4A=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaR/n9q0MINb+cB2dSU3TXvjw+UhN3luvzj9YP+PhL6+t aozuD1cOkpZGMQ4GGTFFFl2rLBcofZHTUvixq9imDmsTCBDGLg4BWAi13MZ/rs697bVfZg5uWmJ z0tVj6MKWl5/fJZzajhovJz/UP/bvR5GhrXrpga9n+cZlm9Ud7FdfMvqVZmLM5P1WI0NdY7Etbs y8wEA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-Originating-IP: [172.25.6.134] X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=MLNgmNZl c=1 sm=1 tr=0 ts=67f7958d cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=UtEzwyU9vMAA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=-4BdC3WIcRMaicUbabwA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 7PYiT6dWKp4AvHwFIZrhrpypWp_mwwRz X-Proofpoint-ORIG-GUID: 7PYiT6dWKp4AvHwFIZrhrpypWp_mwwRz X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This is currently a callback function which takes no parameters; there's no reason for this so let's make it a straightforward value in pvr_fw_defs. Signed-off-by: Matt Coster Reviewed-by: Frank Binns --- Changes in v6: - Add Frank's Rb - Link to v5: https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-10-e4c46e8280a9@imgtec.com Changes in v5: - None - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-10-d987cf4ca439@imgtec.com Changes in v4: - None - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-10-143b3dbef02f@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-11-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-12-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_fw.c | 2 +- drivers/gpu/drm/imagination/pvr_fw.h | 23 ++++++++--------------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 8 +------- drivers/gpu/drm/imagination/pvr_fw_mips.c | 8 +------- 4 files changed, 11 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c index 17c29b5081f417cccd28909ccca4f9ca9da1b9ca..3441c378d91c61df704bfbfee23488b89b1d4569 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -662,7 +662,7 @@ pvr_fw_process(struct pvr_device *pvr_dev) return PTR_ERR(fw_code_ptr); } - if (pvr_dev->fw_dev.defs->has_fixed_data_addr()) { + if (pvr_dev->fw_dev.defs->has_fixed_data_addr) { u32 base_addr = private_data->base_addr & pvr_dev->fw_dev.fw_heap_info.offset_mask; fw_data_ptr = diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index eead744835726712622d5aba9b3480fe264a089f..180d310074e3585c641e540a9e2576b5ab2a5705 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -166,21 +166,6 @@ struct pvr_fw_defs { */ int (*wrapper_init)(struct pvr_device *pvr_dev); - /** - * @has_fixed_data_addr: - * - * Called to check if firmware fixed data must be loaded at the address given by the - * firmware layout table. - * - * This function is mandatory. - * - * Returns: - * * %true if firmware fixed data must be loaded at the address given by the firmware - * layout table. - * * %false otherwise. - */ - bool (*has_fixed_data_addr)(void); - /** * @irq: FW Interrupt information. * @@ -205,6 +190,14 @@ struct pvr_fw_defs { /** @clear_mask: Value to write to the clear_reg in order to clear FW IRQs. */ u32 clear_mask; } irq; + + /** + * @has_fixed_data_addr: Specify whether the firmware fixed data must be loaded at the + * address given by the firmware layout table. + * + * This value is mandatory. + */ + bool has_fixed_data_addr; }; /** diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c index 892823826bf235362d6ae12b34541cea1e10e1d0..41485769fc7cfb643ce7b0ac814d142fa7e15325 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -532,12 +532,6 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size); } -static bool -pvr_meta_has_fixed_data_addr(void) -{ - return false; -} - const struct pvr_fw_defs pvr_fw_defs_meta = { .init = pvr_meta_init, .fw_process = pvr_meta_fw_process, @@ -545,11 +539,11 @@ const struct pvr_fw_defs pvr_fw_defs_meta = { .vm_unmap = pvr_meta_vm_unmap, .get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset, .wrapper_init = pvr_meta_wrapper_init, - .has_fixed_data_addr = pvr_meta_has_fixed_data_addr, .irq = { .status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS, .status_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, + .has_fixed_data_addr = false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c index 567251a663de1dd179159c27288308364619e8dc..5feae0dc85ab51cb3c4e67885bf53cf88d8fa531 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -225,12 +225,6 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } -static bool -pvr_mips_has_fixed_data_addr(void) -{ - return true; -} - const struct pvr_fw_defs pvr_fw_defs_mips = { .init = pvr_mips_init, .fini = pvr_mips_fini, @@ -239,11 +233,11 @@ const struct pvr_fw_defs pvr_fw_defs_mips = { .vm_unmap = pvr_vm_mips_unmap, .get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset, .wrapper_init = pvr_mips_wrapper_init, - .has_fixed_data_addr = pvr_mips_has_fixed_data_addr, .irq = { .status_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, .status_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, .clear_mask = ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, }, + .has_fixed_data_addr = true, };