diff mbox series

drm/radeon: ERROR: "(foo*)" should be "(foo *)"

Message ID 26d3424f83f1f394614e2a774d1bf1e9@208suo.com (mailing list archive)
State New, archived
Headers show
Series drm/radeon: ERROR: "(foo*)" should be "(foo *)" | expand

Commit Message

shijie001@208suo.com July 14, 2023, 5:35 a.m. UTC
Fix one occurrence of the checkpatch.pl error:
ERROR: "(foo*)" should be "(foo *)"

Signed-off-by: Jie Shi <shijie001@208suo.com>
---
  drivers/gpu/drm/radeon/uvd_v1_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Christian König July 14, 2023, 7:21 a.m. UTC | #1
Am 14.07.23 um 07:35 schrieb shijie001@208suo.com:
> Fix one occurrence of the checkpatch.pl error:
> ERROR: "(foo*)" should be "(foo *)"

It's nice to see all those little typos fixed, but I'm not sure how 
feasible it is to send patches for each type individually.

Maybe just merge them together into one patch for the whole radeon code 
base.

Additional to that I'm pretty sure that most of that stuff is already 
fixed, so what base do you use for this?

Regards,
Christian.

>
> Signed-off-by: Jie Shi <shijie001@208suo.com>
> ---
>  drivers/gpu/drm/radeon/uvd_v1_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c 
> b/drivers/gpu/drm/radeon/uvd_v1_0.c
> index 58557c2263a7..5684639d20a6 100644
> --- a/drivers/gpu/drm/radeon/uvd_v1_0.c
> +++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
> @@ -142,7 +142,7 @@ int uvd_v1_0_resume(struct radeon_device *rdev)
>      addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
>      WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
>
> -    WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));
> +    WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));
>
>      return 0;
>  }
diff mbox series

Patch

diff --git a/drivers/gpu/drm/radeon/uvd_v1_0.c 
b/drivers/gpu/drm/radeon/uvd_v1_0.c
index 58557c2263a7..5684639d20a6 100644
--- a/drivers/gpu/drm/radeon/uvd_v1_0.c
+++ b/drivers/gpu/drm/radeon/uvd_v1_0.c
@@ -142,7 +142,7 @@  int uvd_v1_0_resume(struct radeon_device *rdev)
      addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
      WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));

-    WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));
+    WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));

      return 0;
  }