| Message ID | 4bb77a9793d4ba25bf633eff6abe41910bb7fc3c.1488876832.git-series.maxime.ripard@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Maxime, On Tue, Mar 7, 2017 at 7:56 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > The video PLLs are used directly by the HDMI controller. Export them so > that we can use them in our DT node. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > drivers/clk/sunxi-ng/ccu-sun5i.h | 6 ++++-- > include/dt-bindings/clock/sun5i-ccu.h | 3 +++ > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h > index 8144487eb7ca..16f7aa92957e 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun5i.h > +++ b/drivers/clk/sunxi-ng/ccu-sun5i.h > @@ -28,15 +28,17 @@ > #define CLK_PLL_AUDIO_4X 6 > #define CLK_PLL_AUDIO_8X 7 > #define CLK_PLL_VIDEO0 8 > -#define CLK_PLL_VIDEO0_2X 9 > + > +/* The PLL_VIDEO0_2X is exported for HDMI */ > + > #define CLK_PLL_VE 10 > #define CLK_PLL_DDR_BASE 11 > #define CLK_PLL_DDR 12 > #define CLK_PLL_DDR_OTHER 13 > #define CLK_PLL_PERIPH 14 > #define CLK_PLL_VIDEO1 15 > -#define CLK_PLL_VIDEO1_2X 16 > > +/* The PLL_VIDEO0_2X is exported for HDMI */ PLL_VIDEO*1*_2X, right? > /* The CPU clock is exported */ > > #define CLK_AXI 18 Thanks,
Hi Julian, On Tue, Mar 07, 2017 at 09:21:19PM +1100, Julian Calaby wrote: > Hi Maxime, > > On Tue, Mar 7, 2017 at 7:56 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > The video PLLs are used directly by the HDMI controller. Export them so > > that we can use them in our DT node. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > --- > > drivers/clk/sunxi-ng/ccu-sun5i.h | 6 ++++-- > > include/dt-bindings/clock/sun5i-ccu.h | 3 +++ > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h > > index 8144487eb7ca..16f7aa92957e 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sun5i.h > > +++ b/drivers/clk/sunxi-ng/ccu-sun5i.h > > @@ -28,15 +28,17 @@ > > #define CLK_PLL_AUDIO_4X 6 > > #define CLK_PLL_AUDIO_8X 7 > > #define CLK_PLL_VIDEO0 8 > > -#define CLK_PLL_VIDEO0_2X 9 > > + > > +/* The PLL_VIDEO0_2X is exported for HDMI */ > > + > > #define CLK_PLL_VE 10 > > #define CLK_PLL_DDR_BASE 11 > > #define CLK_PLL_DDR 12 > > #define CLK_PLL_DDR_OTHER 13 > > #define CLK_PLL_PERIPH 14 > > #define CLK_PLL_VIDEO1 15 > > -#define CLK_PLL_VIDEO1_2X 16 > > > > +/* The PLL_VIDEO0_2X is exported for HDMI */ > > PLL_VIDEO*1*_2X, right? Good catch, I'll fix it. Thanks! Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h index 8144487eb7ca..16f7aa92957e 100644 --- a/drivers/clk/sunxi-ng/ccu-sun5i.h +++ b/drivers/clk/sunxi-ng/ccu-sun5i.h @@ -28,15 +28,17 @@ #define CLK_PLL_AUDIO_4X 6 #define CLK_PLL_AUDIO_8X 7 #define CLK_PLL_VIDEO0 8 -#define CLK_PLL_VIDEO0_2X 9 + +/* The PLL_VIDEO0_2X is exported for HDMI */ + #define CLK_PLL_VE 10 #define CLK_PLL_DDR_BASE 11 #define CLK_PLL_DDR 12 #define CLK_PLL_DDR_OTHER 13 #define CLK_PLL_PERIPH 14 #define CLK_PLL_VIDEO1 15 -#define CLK_PLL_VIDEO1_2X 16 +/* The PLL_VIDEO0_2X is exported for HDMI */ /* The CPU clock is exported */ #define CLK_AXI 18 diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h index aeb2e2f781fb..81f34d477aeb 100644 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ b/include/dt-bindings/clock/sun5i-ccu.h @@ -19,6 +19,9 @@ #define CLK_HOSC 1 +#define CLK_PLL_VIDEO0_2X 9 + +#define CLK_PLL_VIDEO1_2X 16 #define CLK_CPU 17 #define CLK_AHB_OTG 23
The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- drivers/clk/sunxi-ng/ccu-sun5i.h | 6 ++++-- include/dt-bindings/clock/sun5i-ccu.h | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-)