| Message ID | 534E5658.5090404@vodafone.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Apr 16, 2014 at 12:07:20PM +0200, Christian König wrote: > Hi Borislav, > > thanks for the logs, those were indeed quite helpful. > > Attached are two patches, the first one tries to solve the problem by > increasing the accuracy of the parameters if we don't match exactly and the > second improves the logging of the calculation process by dumping a bunch of > intermediate values used. > > Please apply both on top of my drm-fixes-3.15-wip branch you are already > using, if the first one doesn't solve the problem then please provide new > dmesg logs with drm.debug=0xE. Yes, it works fine! Tested-by: Borislav Petkov <bp@suse.de> Thanks for fixing it. [ 3.634510] [drm] Initialized drm 1.1.0 20060810 [ 6.146795] [drm] radeon kernel modesetting enabled. [ 6.157513] [drm] initializing kernel modesetting (RV635 0x1002:0x9598 0x1043:0x01DA). [ 6.165881] [drm] register mmio base: 0xFEA20000 [ 6.170632] [drm] register mmio size: 65536 [ 6.195783] [drm] Detected VRAM RAM=512M, BAR=256M [ 6.200632] [drm] RAM width 128bits DDR [ 6.245839] [drm] radeon: 512M of VRAM memory ready [ 6.250935] [drm] radeon: 512M of GTT memory ready. [ 6.255995] [drm] Loading RV635 Microcode [ 6.285403] [drm] Internal thermal controller without fan control [ 7.256600] [drm] radeon: power management initialized [ 7.261872] [drm] GART: num cpu pages 131072, num gpu pages 131072 [ 7.268795] [drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0 [ 7.312314] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 7.334860] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 7.341562] [drm] Driver supports precise vblank timestamp query. [ 7.358166] [drm] radeon: irq initialized. [ 7.394139] [drm] ring test on 0 succeeded in 0 usecs [ 7.400078] [drm] ib test on ring 0 succeeded in 0 usecs [ 7.406302] [drm] Radeon Display Connectors [ 7.410553] [drm] Connector 0: [ 7.413654] [drm] DVI-I-1 [ 7.416528] [drm] HPD1 [ 7.419120] [drm] DDC: 0x7e50 0x7e50 0x7e54 0x7e54 0x7e58 0x7e58 0x7e5c 0x7e5c [ 7.426580] [drm] Encoders: [ 7.429621] [drm] DFP1: INTERNAL_UNIPHY [ 7.433862] [drm] CRT2: INTERNAL_KLDSCP_DAC2 [ 7.438526] [drm] Connector 1: [ 7.441622] [drm] DIN-1 [ 7.444333] [drm] Encoders: [ 7.447346] [drm] TV1: INTERNAL_KLDSCP_DAC2 [ 7.451919] [drm] Connector 2: [ 7.455031] [drm] DVI-I-2 [ 7.457890] [drm] HPD2 [ 7.460469] [drm] DDC: 0x7e40 0x7e40 0x7e44 0x7e44 0x7e48 0x7e48 0x7e4c 0x7e4c [ 7.467926] [drm] Encoders: [ 7.470940] [drm] CRT1: INTERNAL_KLDSCP_DAC1 [ 7.475602] [drm] DFP2: INTERNAL_KLDSCP_LVTMA [ 7.557323] [drm] fb mappable at 0xC0141000 [ 7.561555] [drm] vram apper at 0xC0000000 [ 7.565716] [drm] size 9216000 [ 7.568825] [drm] fb depth is 24 [ 7.572103] [drm] pitch is 7680 [ 7.576458] fbcon: radeondrmfb (fb0) is primary device [ 7.842341] radeon 0000:01:00.0: fb0: radeondrmfb frame buffer device [ 7.854344] [drm] Initialized radeon 2.38.0 20080528 for 0000:01:00.0 on minor 0
From e0e6fa5c0b7df9a3de1784082a878bcfebb8a941 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> Date: Wed, 16 Apr 2014 11:57:28 +0200 Subject: [PATCH 2/2] drm/radeon: improve logging of PLL parameter calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/radeon/radeon_display.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index fb3b505..037db45 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -820,6 +820,9 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den, { unsigned tmp; + DRM_DEBUG_KMS("nom: %d den: %d nom_min %d den_min %d\n", + *nom, *den, nom_min, den_min); + /* reduce the numbers to a simpler ratio */ tmp = gcd(*nom, *den); *nom /= tmp; @@ -876,6 +879,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, fb_div_max *= 10; } + DRM_DEBUG_KMS("fb_div_min: %d fb_div_max: %d\n", + fb_div_min, fb_div_max); + /* determine allowed ref divider range */ if (pll->flags & RADEON_PLL_USE_REF_DIV) ref_div_min = pll->reference_div; @@ -883,6 +889,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, ref_div_min = pll->min_ref_div; ref_div_max = pll->max_ref_div; + DRM_DEBUG_KMS("ref_div_min: %d ref_div_max: %d\n", + ref_div_min, ref_div_max); + /* determine allowed post divider range */ if (pll->flags & RADEON_PLL_USE_POST_DIV) { post_div_min = pll->post_div; @@ -912,6 +921,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, post_div_max = pll->max_post_div; } + DRM_DEBUG_KMS("post_div_min: %d post_div_max: %d\n", + post_div_min, post_div_max); + /* represent the searched ratio as fractional number */ nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10; den = pll->reference_freq; @@ -980,7 +992,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, *post_div_p = post_div; DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", - freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p, + freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, ref_div, post_div); } -- 1.9.1