From patchwork Tue Sep 2 07:34:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Michel_D=C3=A4nzer?= X-Patchwork-Id: 4823101 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5DB3DC0338 for ; Tue, 2 Sep 2014 07:34:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3D094201B4 for ; Tue, 2 Sep 2014 07:34:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9BE6A201CD for ; Tue, 2 Sep 2014 07:34:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E7C66E41B; Tue, 2 Sep 2014 00:34:11 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.gna.ch (darkcity.gna.ch [195.226.6.51]) by gabe.freedesktop.org (Postfix) with ESMTP id ECC546E41B for ; Tue, 2 Sep 2014 00:34:10 -0700 (PDT) Received: from thor (125-14-38-183.rev.home.ne.jp [125.14.38.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by darkcity.gna.ch (Postfix) with ESMTPSA id 67AB5C0307; Tue, 2 Sep 2014 09:33:49 +0200 (CEST) Received: from localhost ([127.0.0.1]) by thor with esmtp (Exim 4.84) (envelope-from ) id 1XOibN-0008LB-Ho; Tue, 02 Sep 2014 16:34:05 +0900 Message-ID: <540572EC.4070909@daenzer.net> Date: Tue, 02 Sep 2014 16:34:04 +0900 From: =?windows-1252?Q?Michel_D=E4nzer?= User-Agent: Mozilla/5.0 (X11; Linux ppc; rv:31.0) Gecko/20100101 Icedove/31.0 MIME-Version: 1.0 To: Mikael Pettersson Subject: Re: [BISECTED] 3.17-rc1 radeon screen corruption due to "Always flush the HDP cache before submitting a CS to the GPU" References: <21505.55482.547592.906934@gargle.gargle.HOWL> In-Reply-To: <21505.55482.547592.906934@gargle.gargle.HOWL> Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 30.08.2014 22:59, Mikael Pettersson wrote: > Since 3.17-rc1 my radeon card (RV370 / X1050 card) causes screen corruption > after a while in X + firefox. This still occurs with yesterday's HEAD > of Linus' repo. 3.16 and ealier kernels are fine. > > I ran a bisect, which identified: > > commit 72a9987edcedb89db988079a03c9b9c65b6ec9ac > Author: Michel Dänzer > Date: Thu Jul 31 18:43:49 2014 +0900 > > drm/radeon: Always flush the HDP cache before submitting a CS to the GPU > > as the cause of my screen corruption. Reverting this from 3.17-rc2 > (which requires manual intervention due to subsequent changes in > radeon_ring_commit()) eliminates the screen corruption. Does the patch below help? diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 4c5ec44..3ff9c53 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -1070,6 +1070,20 @@ void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) radeon_ring_write(ring, rdev->config.r100.hdp_cntl); } +/** + * r100_mmio_hdp_flush - flush Host Data Path via MMIO + * rdev: radeon device structure + */ +void r100_mmio_hdp_flush(struct radeon_device *rdev) +{ + WREG32(RADEON_HOST_PATH_CNTL, + rdev->config.r100.hdp_cntl | RADEON_HDP_READ_BUFFER_INVALIDATE); + (void)RREG32(RADEON_HOST_PATH_CNTL); + WREG32(RADEON_HOST_PATH_CNTL, + rdev->config.r100.hdp_cntl); + (void)RREG32(RADEON_HOST_PATH_CNTL); +} + static void r100_cp_load_microcode(struct radeon_device *rdev) { const __be32 *fw_data; diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index eeeeabe..c23a123 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -408,7 +408,7 @@ static struct radeon_asic r300_asic_pcie = { .resume = &r300_resume, .vga_set_state = &r100_vga_set_state, .asic_reset = &r300_asic_reset, - .mmio_hdp_flush = NULL, + .mmio_hdp_flush = r100_mmio_hdp_flush, .gui_idle = &r100_gui_idle, .mc_wait_for_idle = &r300_mc_wait_for_idle, .gart = { diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 275a5dc..e9b1c35 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -150,6 +150,8 @@ void r100_gfx_set_wptr(struct radeon_device *rdev, struct radeon_ring *ring); void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring); +void r100_mmio_hdp_flush(struct radeon_device *rdev); + /* * r200,rv250,rs300,rv280 */ diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index bfd7e1b..3d0f564 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -368,6 +368,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, r = radeon_bo_wait(robj, &cur_placement, false); /* Flush HDP cache via MMIO if necessary */ if (rdev->asic->mmio_hdp_flush && + !rdev->asic->ring[RADEON_RING_TYPE_GFX_INDEX]->hdp_flush && radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) robj->rdev->asic->mmio_hdp_flush(rdev); drm_gem_object_unreference_unlocked(gobj); diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index d656079..b82843b 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -188,7 +188,8 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, /* If we are emitting the HDP flush via the ring buffer, we need to * do it before padding. */ - if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush) + if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush && + !rdev->asic->mmio_hdp_flush) rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring); /* We pad to match fetch size */ while (ring->wptr & ring->align_mask) {