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Tue, 2 Jul 2024 12:24:41 +0000 From: Sandor Yu To: dmitry.baryshkov@linaro.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, vkoul@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, mripard@kernel.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, Sandor.yu@nxp.com, oliver.brown@nxp.com, alexander.stein@ew.tq-group.com, sam@ravnborg.org Subject: [PATCH v16 7/8] arm64: dts: imx8mq: Add DCSS + HDMI/DP display pipeline Date: Tue, 2 Jul 2024 20:22:39 +0800 Message-Id: <727edb97281798454951ddf03cfdab5a428bc9de.1719903904.git.Sandor.yu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: X-ClientProxiedBy: SI1PR02CA0031.apcprd02.prod.outlook.com (2603:1096:4:1f6::11) To PAXPR04MB9448.eurprd04.prod.outlook.com (2603:10a6:102:2b1::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9448:EE_|AM7PR04MB6870:EE_ X-MS-Office365-Filtering-Correlation-Id: e42357eb-e1d6-41ac-eb6c-08dc9a91f2ba X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PHY mode (DP/HDMI) is selected by the connector type connected to mhdp port@1 endpoint. Signed-off-by: Alexander Stein --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index e03186bbc415..6bd7d2b2aba2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1602,6 +1602,74 @@ aips4: bus@32c00000 { /* AIPS4 */ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + mdhp_phy: phy@32c00000 { + compatible = "fsl,imx8mq-hdptx-phy"; + reg = <0x32c00000 0x100000>; + #phy-cells = <0>; + clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ref", "apb"; + }; + + mhdp: bridge@32c00000 { + compatible = "fsl,imx8mq-mhdp8501"; + reg = <0x32c00000 0x100000>; + interrupts = , + ; + interrupt-names = "plug_in", "plug_out"; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + phys = <&mdhp_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mhdp_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; + + port@1 { + reg = <1>; + + mhdp_out: endpoint { + }; + }; + }; + }; + + dcss: display-controller@32e00000 { + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupt-parent = <&irqsteer>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + + port { + dcss_out: endpoint { + remote-endpoint = <&mhdp_in>; + }; + }; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>;