[v2,05/10] drm/fourcc: Add DRM_FORMAT_C[124]

Commit Message

Geert Uytterhoeven March 7, 2022, 8:52 p.m. UTC

Introduce fourcc codes for color-indexed frame buffer formats with two,
four, and sixteen colors, and provide a mapping from bit per pixel and
depth to fourcc codes.

As the number of bits per pixel is less than eight, these rely on proper
block handling for the calculation of bits per pixel and pitch.

Signed-off-by: Geert Uytterhoeven <[e-mail]>
---
v2:
  - Improve pixel descriptions,
  - Require depth to match bpp in drm_mode_legacy_fb_format(),
  - Set .is_color_indexed flag.
---
 drivers/gpu/drm/drm_fourcc.c  | 21 +++++++++++++++++++++
 include/uapi/drm/drm_fourcc.h |  5 ++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

Comments

Pekka Paalanen March 8, 2022, 9:04 a.m. UTC | #1

On Mon,  7 Mar 2022 21:52:40 +0100
Geert Uytterhoeven <[e-mail]> wrote:

> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen colors, and provide a mapping from bit per pixel and
> depth to fourcc codes.
> 
> As the number of bits per pixel is less than eight, these rely on proper
> block handling for the calculation of bits per pixel and pitch.
> 
> Signed-off-by: Geert Uytterhoeven <[e-mail]>
> ---
> v2:
>   - Improve pixel descriptions,
>   - Require depth to match bpp in drm_mode_legacy_fb_format(),
>   - Set .is_color_indexed flag.
> ---
>  drivers/gpu/drm/drm_fourcc.c  | 21 +++++++++++++++++++++
>  include/uapi/drm/drm_fourcc.h |  5 ++++-
>  2 files changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 6c76bd821d17e7c7..29f4fe199c4ddcf0 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -43,6 +43,21 @@ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
>  	uint32_t fmt = DRM_FORMAT_INVALID;
>  
>  	switch (bpp) {
> +	case 1:
> +		if (depth == 1)
> +			fmt = DRM_FORMAT_C1;
> +		break;
> +
> +	case 2:
> +		if (depth == 2)
> +			fmt = DRM_FORMAT_C2;
> +		break;
> +
> +	case 4:
> +		if (depth == 4)
> +			fmt = DRM_FORMAT_C4;
> +		break;
> +
>  	case 8:
>  		if (depth == 8)
>  			fmt = DRM_FORMAT_C8;
> @@ -132,6 +147,12 @@ EXPORT_SYMBOL(drm_driver_legacy_fb_format);
>  const struct drm_format_info *__drm_format_info(u32 format)
>  {
>  	static const struct drm_format_info formats[] = {
> +		{ .format = DRM_FORMAT_C1,		.depth = 1,  .num_planes = 1,
> +		  .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
> +		{ .format = DRM_FORMAT_C2,		.depth = 2,  .num_planes = 1,
> +		  .char_per_block = { 1, }, .block_w = { 4, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
> +		{ .format = DRM_FORMAT_C4,		.depth = 4,  .num_planes = 1,
> +		  .char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
>  		{ .format = DRM_FORMAT_C8,		.depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
>  		{ .format = DRM_FORMAT_R8,		.depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
>  		{ .format = DRM_FORMAT_R10,		.depth = 10, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index fc0c1454d2757d5d..457ed39cc48f08e1 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -99,7 +99,10 @@ extern "C" {
>  #define DRM_FORMAT_INVALID	0
>  
>  /* color index */
> -#define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> +#define DRM_FORMAT_C1		fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> +#define DRM_FORMAT_C2		fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> +#define DRM_FORMAT_C4		fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> +#define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
>  
>  /* 8 bpp Red */
>  #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */

Hi Geert,

this patch looks good to me, so

Reviewed-by: Pekka Paalanen <[e-mail]>


Thanks,
pq

Javier Martinez Canillas March 9, 2022, 12:57 p.m. UTC | #2

On 3/7/22 21:52, Geert Uytterhoeven wrote:
> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen colors, and provide a mapping from bit per pixel and
> depth to fourcc codes.
> 
> As the number of bits per pixel is less than eight, these rely on proper
> block handling for the calculation of bits per pixel and pitch.
> 
> Signed-off-by: Geert Uytterhoeven <[e-mail]>
> ---

Reviewed-by: Javier Martinez Canillas <[e-mail]>

Geert Uytterhoeven March 14, 2022, 1:30 p.m. UTC | #3

On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:
> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen colors, and provide a mapping from bit per pixel and
> depth to fourcc codes.
>
> As the number of bits per pixel is less than eight, these rely on proper
> block handling for the calculation of bits per pixel and pitch.
>
> Signed-off-by: Geert Uytterhoeven <[e-mail]>

> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -99,7 +99,10 @@ extern "C" {
>  #define DRM_FORMAT_INVALID     0
>
>  /* color index */
> -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
>
>  /* 8 bpp Red */
>  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */

After replying to Ilia's comment[1], I realized the CFB drawing
operations use native byte and bit ordering, unless
FBINFO_FOREIGN_ENDIAN is set.
While Amiga, Atari, and Sun-3 use big-endian bit ordering,
e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
(sh7760fb configures ordering to match host order).
BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
guess they are broken on big-endian.
Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
on little-endian.

Hence the above should become:

    #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
[7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
    #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
[7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
    #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
[7:0] C1:C0 4:4 two pixels/byte */

The same changes should be made for DRM_FORMAT_[RD][124].

The fbdev emulation code should gain support for these with and without
DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?

[1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
[2] See p.30 of the VIDC datasheet
    http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
[3] See p.1178 of the SH7660 datasheet
    https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Pekka Paalanen March 14, 2022, 3:05 p.m. UTC | #4

On Mon, 14 Mar 2022 14:30:18 +0100
Geert Uytterhoeven <[e-mail]> wrote:

> On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:
> > Introduce fourcc codes for color-indexed frame buffer formats with two,
> > four, and sixteen colors, and provide a mapping from bit per pixel and
> > depth to fourcc codes.
> >
> > As the number of bits per pixel is less than eight, these rely on proper
> > block handling for the calculation of bits per pixel and pitch.
> >
> > Signed-off-by: Geert Uytterhoeven <[e-mail]>  
> 
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -99,7 +99,10 @@ extern "C" {
> >  #define DRM_FORMAT_INVALID     0
> >
> >  /* color index */
> > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> >
> >  /* 8 bpp Red */
> >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */  
> 
> After replying to Ilia's comment[1], I realized the CFB drawing
> operations use native byte and bit ordering, unless
> FBINFO_FOREIGN_ENDIAN is set.
> While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> (sh7760fb configures ordering to match host order).
> BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> guess they are broken on big-endian.
> Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> on little-endian.
> 
> Hence the above should become:
> 
>     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
>     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
>     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> [7:0] C1:C0 4:4 two pixels/byte */
> 
> The same changes should be made for DRM_FORMAT_[RD][124].
> 
> The fbdev emulation code should gain support for these with and without
> DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> 
> [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> [2] See p.30 of the VIDC datasheet
>     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> [3] See p.1178 of the SH7660 datasheet
>     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf

Hi Geert,

why would CPU endianess affect the order of bits in a byte?

Do you mean that bit 0 one machine is (1 << 0), and on another machine
bit 0 is (1 << 7)?

In C, we have only one way to address bits of a byte and that is with
arithmetic. You cannot take the address of a bit any other way, can you?

Can we standardise on "bit n of a byte is addressed as (1 << n)"?

I don't mind in which order the pixels are inside a byte, as long as it
doesn't change by CPU endianess. If you need both directions, then use
two different drm_fourcc codes that do not change their meaning by CPU
endianess. Just like we have XRGB and BGRX formats.

I would not like to see DRM_FORMAT_BIG_ENDIAN used for this, it would
conflate a whole new concept into the mess that is little- vs.
big-endian.


Thanks,
pq

Geert Uytterhoeven March 14, 2022, 7:01 p.m. UTC | #5

Hi Pekka,

On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:
> On Mon, 14 Mar 2022 14:30:18 +0100
> Geert Uytterhoeven <[e-mail]> wrote:
> > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:
> > > Introduce fourcc codes for color-indexed frame buffer formats with two,
> > > four, and sixteen colors, and provide a mapping from bit per pixel and
> > > depth to fourcc codes.
> > >
> > > As the number of bits per pixel is less than eight, these rely on proper
> > > block handling for the calculation of bits per pixel and pitch.
> > >
> > > Signed-off-by: Geert Uytterhoeven <[e-mail]>
> >
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -99,7 +99,10 @@ extern "C" {
> > >  #define DRM_FORMAT_INVALID     0
> > >
> > >  /* color index */
> > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > >
> > >  /* 8 bpp Red */
> > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
> >
> > After replying to Ilia's comment[1], I realized the CFB drawing
> > operations use native byte and bit ordering, unless
> > FBINFO_FOREIGN_ENDIAN is set.
> > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > (sh7760fb configures ordering to match host order).
> > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > guess they are broken on big-endian.
> > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > on little-endian.
> >
> > Hence the above should become:
> >
> >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > [7:0] C1:C0 4:4 two pixels/byte */
> >
> > The same changes should be made for DRM_FORMAT_[RD][124].
> >
> > The fbdev emulation code should gain support for these with and without
> > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> >
> > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > [2] See p.30 of the VIDC datasheet
> >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > [3] See p.1178 of the SH7660 datasheet
> >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf
>
> why would CPU endianess affect the order of bits in a byte?

It doesn't, but see below.

> Do you mean that bit 0 one machine is (1 << 0), and on another machine
> bit 0 is (1 << 7)?

No, I mean that in case of multiple pixels per byte, the display
hardware pumps out pixels to the CRTC starting from either the MSB
or the LSB of the first display byte.  Which order depends on the
display hardware, not on the CPU.

> In C, we have only one way to address bits of a byte and that is with
> arithmetic. You cannot take the address of a bit any other way, can you?
>
> Can we standardise on "bit n of a byte is addressed as (1 << n)"?

BIT(n) in Linux works the same for little- and big-endian CPUs.
But display hardware may use a different bit order.

> I don't mind in which order the pixels are inside a byte, as long as it
> doesn't change by CPU endianess. If you need both directions, then use
> two different drm_fourcc codes that do not change their meaning by CPU
> endianess. Just like we have XRGB and BGRX formats.

OK.

> I would not like to see DRM_FORMAT_BIG_ENDIAN used for this, it would
> conflate a whole new concept into the mess that is little- vs.
> big-endian.

OK.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Finn Thain March 14, 2022, 10:15 p.m. UTC | #6

Hi Geert,

On Mon, 14 Mar 2022, Geert Uytterhoeven wrote:

> On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:
> > On Mon, 14 Mar 2022 14:30:18 +0100
> > Geert Uytterhoeven <[e-mail]> wrote:
> > > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:
> > > > Introduce fourcc codes for color-indexed frame buffer formats with 
> > > > two, four, and sixteen colors, and provide a mapping from bit per 
> > > > pixel and depth to fourcc codes.
> > > >
> > > > As the number of bits per pixel is less than eight, these rely on 
> > > > proper block handling for the calculation of bits per pixel and 
> > > > pitch.
> > > >
> > > > Signed-off-by: Geert Uytterhoeven <[e-mail]>
> > >
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -99,7 +99,10 @@ extern "C" {
> > > >  #define DRM_FORMAT_INVALID     0
> > > >
> > > >  /* color index */
> > > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > > >
> > > >  /* 8 bpp Red */
> > > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
> > >
> > > After replying to Ilia's comment[1], I realized the CFB drawing
> > > operations use native byte and bit ordering, unless
> > > FBINFO_FOREIGN_ENDIAN is set.
> > > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > > (sh7760fb configures ordering to match host order).
> > > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > > guess they are broken on big-endian.
> > > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > > on little-endian.
> > >
> > > Hence the above should become:
> > >
> > >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> > >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> > >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > > [7:0] C1:C0 4:4 two pixels/byte */
> > >
> > > The same changes should be made for DRM_FORMAT_[RD][124].
> > >
> > > The fbdev emulation code should gain support for these with and without
> > > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> > >
> > > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > > [2] See p.30 of the VIDC datasheet
> > >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > > [3] See p.1178 of the SH7660 datasheet
> > >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf
> >
> > why would CPU endianess affect the order of bits in a byte?
> 
> It doesn't, but see below.
> 
> > Do you mean that bit 0 one machine is (1 << 0), and on another machine
> > bit 0 is (1 << 7)?
> 
> No, I mean that in case of multiple pixels per byte, the display
> hardware pumps out pixels to the CRTC starting from either the MSB
> or the LSB of the first display byte.  Which order depends on the
> display hardware, not on the CPU.
> 
> > In C, we have only one way to address bits of a byte and that is with
> > arithmetic. You cannot take the address of a bit any other way, can you?
> >
> > Can we standardise on "bit n of a byte is addressed as (1 << n)"?
> 
> BIT(n) in Linux works the same for little- and big-endian CPUs.
> But display hardware may use a different bit order.
> 

Perhaps some of this confusion could be avoided if you describe the 
problem in terms of the sequence of scan-out of pixels, rather than in 
terms of the serialization of bits. The significance of bits within each 
pixel and the ordering of pixels within each memory word are independent, 
right?

Pekka Paalanen March 15, 2022, 7:32 a.m. UTC | #7

On Tue, 15 Mar 2022 09:15:08 +1100 (AEDT)
Finn Thain <[e-mail]> wrote:

> Hi Geert,
> 
> On Mon, 14 Mar 2022, Geert Uytterhoeven wrote:
> 
> > On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:  
> > > On Mon, 14 Mar 2022 14:30:18 +0100
> > > Geert Uytterhoeven <[e-mail]> wrote:  
> > > > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:  
> > > > > Introduce fourcc codes for color-indexed frame buffer formats with 
> > > > > two, four, and sixteen colors, and provide a mapping from bit per 
> > > > > pixel and depth to fourcc codes.
> > > > >
> > > > > As the number of bits per pixel is less than eight, these rely on 
> > > > > proper block handling for the calculation of bits per pixel and 
> > > > > pitch.
> > > > >
> > > > > Signed-off-by: Geert Uytterhoeven <[e-mail]>  
> > > >  
> > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > @@ -99,7 +99,10 @@ extern "C" {
> > > > >  #define DRM_FORMAT_INVALID     0
> > > > >
> > > > >  /* color index */
> > > > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > > > >
> > > > >  /* 8 bpp Red */
> > > > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */  
> > > >
> > > > After replying to Ilia's comment[1], I realized the CFB drawing
> > > > operations use native byte and bit ordering, unless
> > > > FBINFO_FOREIGN_ENDIAN is set.
> > > > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > > > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > > > (sh7760fb configures ordering to match host order).
> > > > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > > > guess they are broken on big-endian.
> > > > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > > > on little-endian.
> > > >
> > > > Hence the above should become:
> > > >
> > > >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > > > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > > > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> > > >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > > > [7:0] C1:C0 4:4 two pixels/byte */
> > > >
> > > > The same changes should be made for DRM_FORMAT_[RD][124].
> > > >
> > > > The fbdev emulation code should gain support for these with and without
> > > > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> > > >
> > > > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > > > [2] See p.30 of the VIDC datasheet
> > > >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > > > [3] See p.1178 of the SH7660 datasheet
> > > >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf  
> > >
> > > why would CPU endianess affect the order of bits in a byte?  
> > 
> > It doesn't, but see below.
> >   
> > > Do you mean that bit 0 one machine is (1 << 0), and on another machine
> > > bit 0 is (1 << 7)?  
> > 
> > No, I mean that in case of multiple pixels per byte, the display
> > hardware pumps out pixels to the CRTC starting from either the MSB
> > or the LSB of the first display byte.  Which order depends on the
> > display hardware, not on the CPU.
> >   
> > > In C, we have only one way to address bits of a byte and that is with
> > > arithmetic. You cannot take the address of a bit any other way, can you?
> > >
> > > Can we standardise on "bit n of a byte is addressed as (1 << n)"?  
> > 
> > BIT(n) in Linux works the same for little- and big-endian CPUs.
> > But display hardware may use a different bit order.
> >   
> 
> Perhaps some of this confusion could be avoided if you describe the 
> problem in terms of the sequence of scan-out of pixels, rather than in 
> terms of the serialization of bits. The significance of bits within each 
> pixel and the ordering of pixels within each memory word are independent, 
> right?

Yes, that might help.

Also, when drm_fourcc.h is describing pixel formats, it needs to
consider only how a little-endian CPU accesses them. That's how pixel
data in memory is described. Display hardware plays no part in that.
It is the driver's job to expose the pixel formats that match display
hardware behaviour.


Thanks,
pq

Geert Uytterhoeven March 15, 2022, 7:51 a.m. UTC | #8

Hi Pekka,

On Tue, Mar 15, 2022 at 8:33 AM Pekka Paalanen <[e-mail]> wrote:
> On Tue, 15 Mar 2022 09:15:08 +1100 (AEDT)
> Finn Thain <[e-mail]> wrote:
> > On Mon, 14 Mar 2022, Geert Uytterhoeven wrote:
> > > On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:
> > > > On Mon, 14 Mar 2022 14:30:18 +0100
> > > > Geert Uytterhoeven <[e-mail]> wrote:
> > > > > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:
> > > > > > Introduce fourcc codes for color-indexed frame buffer formats with
> > > > > > two, four, and sixteen colors, and provide a mapping from bit per
> > > > > > pixel and depth to fourcc codes.
> > > > > >
> > > > > > As the number of bits per pixel is less than eight, these rely on
> > > > > > proper block handling for the calculation of bits per pixel and
> > > > > > pitch.
> > > > > >
> > > > > > Signed-off-by: Geert Uytterhoeven <[e-mail]>
> > > > >
> > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > @@ -99,7 +99,10 @@ extern "C" {
> > > > > >  #define DRM_FORMAT_INVALID     0
> > > > > >
> > > > > >  /* color index */
> > > > > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > > > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > > > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > > > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > > > > >
> > > > > >  /* 8 bpp Red */
> > > > > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
> > > > >
> > > > > After replying to Ilia's comment[1], I realized the CFB drawing
> > > > > operations use native byte and bit ordering, unless
> > > > > FBINFO_FOREIGN_ENDIAN is set.
> > > > > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > > > > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > > > > (sh7760fb configures ordering to match host order).
> > > > > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > > > > guess they are broken on big-endian.
> > > > > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > > > > on little-endian.
> > > > >
> > > > > Hence the above should become:
> > > > >
> > > > >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > > > > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > > > > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> > > > >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > > > > [7:0] C1:C0 4:4 two pixels/byte */
> > > > >
> > > > > The same changes should be made for DRM_FORMAT_[RD][124].
> > > > >
> > > > > The fbdev emulation code should gain support for these with and without
> > > > > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> > > > >
> > > > > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > > > > [2] See p.30 of the VIDC datasheet
> > > > >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > > > > [3] See p.1178 of the SH7660 datasheet
> > > > >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf
> > > >
> > > > why would CPU endianess affect the order of bits in a byte?
> > >
> > > It doesn't, but see below.
> > >
> > > > Do you mean that bit 0 one machine is (1 << 0), and on another machine
> > > > bit 0 is (1 << 7)?
> > >
> > > No, I mean that in case of multiple pixels per byte, the display
> > > hardware pumps out pixels to the CRTC starting from either the MSB
> > > or the LSB of the first display byte.  Which order depends on the
> > > display hardware, not on the CPU.
> > >
> > > > In C, we have only one way to address bits of a byte and that is with
> > > > arithmetic. You cannot take the address of a bit any other way, can you?
> > > >
> > > > Can we standardise on "bit n of a byte is addressed as (1 << n)"?
> > >
> > > BIT(n) in Linux works the same for little- and big-endian CPUs.
> > > But display hardware may use a different bit order.
> >
> > Perhaps some of this confusion could be avoided if you describe the
> > problem in terms of the sequence of scan-out of pixels, rather than in
> > terms of the serialization of bits. The significance of bits within each
> > pixel and the ordering of pixels within each memory word are independent,
> > right?
>
> Yes, that might help.

Display:

     P0  P1  P2  P3  P4  P5  P6  P7  P8  P9 P10 P11 P12 P13 P14 P15

    P15 P14 P13 P12 P11 P10  P9  P8  P7  P6  P5  P4  P3  P2  P1  P0

Memory:

  1 bpp (MSB first):

              bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
              ---- ---- ---- ---- ---- ---- ---- ----
      byte 0:   P0   P1   P2   P3   P4   P5   P6   P7
      byte 1:   P8   P9  P10  P11  P12  P13  P14  P15

  1 bpp (LSB first):

              bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
              ---- ---- ---- ---- ---- ---- ---- ----
      byte 0:   P7   P6   P5   P4   P3   P2   P1   P0
      byte 1:  P15  P14  P13  P12  P11  P10   P9   P8

  2 bpp (MSB first):

              bits7-6 bits5-4 bits3-2 bits1-0
              ------- ------- ------- -------
      byte 0:    P0      P1      P2      P3
      byte 1:    P4      P5      P6      P7
      byte 2:    P8      P9     P10     P11
      byte 3:   P12     P13     P14     P15

  2 bpp (LSB first):

              bits7-6 bits5-4 bits3-2 bits1-0
              ------- ------- ------- -------
      byte 0:    P3      P2      P1      P0
      byte 1:    P7      P6      P5      P4
      byte 2:   P11     P10      P9      P8
      byte 3:   P15     P14     P13     P12

  4 bpp (MSB first):

              bits7-4 bits3-0
              ------- -------
      byte 0:    P0      P1
      byte 1:    P2      P3
      byte 2:    P4      P5
      byte 3:    P6      P7
      byte 4:    P8      P9
      byte 5:   P10     P11
      byte 6:   P12     P13
      byte 7:   P14     P15

  4 bpp (LSB first):

              bits7-4 bits3-0
              ------- -------
      byte 0:    P1      P0
      byte 1:    P3      P2
      byte 2:    P5      P4
      byte 3:    P7      P6
      byte 4:    P9      P8
      byte 5:   P11     P10
      byte 6:   P13     P12
      byte 7:   P15     P14

> Also, when drm_fourcc.h is describing pixel formats, it needs to
> consider only how a little-endian CPU accesses them. That's how pixel
> data in memory is described. Display hardware plays no part in that.
> It is the driver's job to expose the pixel formats that match display
> hardware behaviour.

But if the "CPU format" does not match the "display support",
all pixel data must be converted?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Geert Uytterhoeven March 15, 2022, 7:52 a.m. UTC | #9

On Tue, Mar 15, 2022 at 8:51 AM Geert Uytterhoeven <[e-mail]> wrote:
> > Also, when drm_fourcc.h is describing pixel formats, it needs to
> > consider only how a little-endian CPU accesses them. That's how pixel
> > data in memory is described. Display hardware plays no part in that.
> > It is the driver's job to expose the pixel formats that match display
> > hardware behaviour.
>
> But if the "CPU format" does not match the "display support",

s/support/format/

> all pixel data must be converted?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Pekka Paalanen March 15, 2022, 8:45 a.m. UTC | #10

On Tue, 15 Mar 2022 08:51:31 +0100
Geert Uytterhoeven <[e-mail]> wrote:

> Hi Pekka,
> 
> On Tue, Mar 15, 2022 at 8:33 AM Pekka Paalanen <[e-mail]> wrote:
> > On Tue, 15 Mar 2022 09:15:08 +1100 (AEDT)
> > Finn Thain <[e-mail]> wrote:  
> > > On Mon, 14 Mar 2022, Geert Uytterhoeven wrote:  
> > > > On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:  
> > > > > On Mon, 14 Mar 2022 14:30:18 +0100
> > > > > Geert Uytterhoeven <[e-mail]> wrote:  
> > > > > > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:  
> > > > > > > Introduce fourcc codes for color-indexed frame buffer formats with
> > > > > > > two, four, and sixteen colors, and provide a mapping from bit per
> > > > > > > pixel and depth to fourcc codes.
> > > > > > >
> > > > > > > As the number of bits per pixel is less than eight, these rely on
> > > > > > > proper block handling for the calculation of bits per pixel and
> > > > > > > pitch.
> > > > > > >
> > > > > > > Signed-off-by: Geert Uytterhoeven <[e-mail]>  
> > > > > >  
> > > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > > @@ -99,7 +99,10 @@ extern "C" {
> > > > > > >  #define DRM_FORMAT_INVALID     0
> > > > > > >
> > > > > > >  /* color index */
> > > > > > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > > > > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > > > > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > > > > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > > > > > >
> > > > > > >  /* 8 bpp Red */
> > > > > > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */  
> > > > > >
> > > > > > After replying to Ilia's comment[1], I realized the CFB drawing
> > > > > > operations use native byte and bit ordering, unless
> > > > > > FBINFO_FOREIGN_ENDIAN is set.
> > > > > > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > > > > > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > > > > > (sh7760fb configures ordering to match host order).
> > > > > > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > > > > > guess they are broken on big-endian.
> > > > > > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > > > > > on little-endian.
> > > > > >
> > > > > > Hence the above should become:
> > > > > >
> > > > > >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > > > > > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > > > > > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> > > > > >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > > > > > [7:0] C1:C0 4:4 two pixels/byte */
> > > > > >
> > > > > > The same changes should be made for DRM_FORMAT_[RD][124].
> > > > > >
> > > > > > The fbdev emulation code should gain support for these with and without
> > > > > > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> > > > > >
> > > > > > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > > > > > [2] See p.30 of the VIDC datasheet
> > > > > >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > > > > > [3] See p.1178 of the SH7660 datasheet
> > > > > >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf  
> > > > >
> > > > > why would CPU endianess affect the order of bits in a byte?  
> > > >
> > > > It doesn't, but see below.
> > > >  
> > > > > Do you mean that bit 0 one machine is (1 << 0), and on another machine
> > > > > bit 0 is (1 << 7)?  
> > > >
> > > > No, I mean that in case of multiple pixels per byte, the display
> > > > hardware pumps out pixels to the CRTC starting from either the MSB
> > > > or the LSB of the first display byte.  Which order depends on the
> > > > display hardware, not on the CPU.
> > > >  
> > > > > In C, we have only one way to address bits of a byte and that is with
> > > > > arithmetic. You cannot take the address of a bit any other way, can you?
> > > > >
> > > > > Can we standardise on "bit n of a byte is addressed as (1 << n)"?  
> > > >
> > > > BIT(n) in Linux works the same for little- and big-endian CPUs.
> > > > But display hardware may use a different bit order.  
> > >
> > > Perhaps some of this confusion could be avoided if you describe the
> > > problem in terms of the sequence of scan-out of pixels, rather than in
> > > terms of the serialization of bits. The significance of bits within each
> > > pixel and the ordering of pixels within each memory word are independent,
> > > right?  
> >
> > Yes, that might help.  
> 
> Display:
> 
>      P0  P1  P2  P3  P4  P5  P6  P7  P8  P9 P10 P11 P12 P13 P14 P15
> 
>     P15 P14 P13 P12 P11 P10  P9  P8  P7  P6  P5  P4  P3  P2  P1  P0

Hi Geert,

does this mean the display hardware emits even rows from left to right
and odd rows from right to left?

I suppose that would practically eliminate the horizontal blanking
period in CRT timings. If so, I think that might be best represented as
a new format modifier.

I'm guessing P stands for "pixel".

> 
> Memory:
> 
>   1 bpp (MSB first):
> 
>               bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
>               ---- ---- ---- ---- ---- ---- ---- ----
>       byte 0:   P0   P1   P2   P3   P4   P5   P6   P7
>       byte 1:   P8   P9  P10  P11  P12  P13  P14  P15
> 
>   1 bpp (LSB first):
> 
>               bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
>               ---- ---- ---- ---- ---- ---- ---- ----
>       byte 0:   P7   P6   P5   P4   P3   P2   P1   P0
>       byte 1:  P15  P14  P13  P12  P11  P10   P9   P8
> 
>   2 bpp (MSB first):
> 
>               bits7-6 bits5-4 bits3-2 bits1-0
>               ------- ------- ------- -------
>       byte 0:    P0      P1      P2      P3
>       byte 1:    P4      P5      P6      P7
>       byte 2:    P8      P9     P10     P11
>       byte 3:   P12     P13     P14     P15
> 
>   2 bpp (LSB first):
> 
>               bits7-6 bits5-4 bits3-2 bits1-0
>               ------- ------- ------- -------
>       byte 0:    P3      P2      P1      P0
>       byte 1:    P7      P6      P5      P4
>       byte 2:   P11     P10      P9      P8
>       byte 3:   P15     P14     P13     P12
> 
>   4 bpp (MSB first):
> 
>               bits7-4 bits3-0
>               ------- -------
>       byte 0:    P0      P1
>       byte 1:    P2      P3
>       byte 2:    P4      P5
>       byte 3:    P6      P7
>       byte 4:    P8      P9
>       byte 5:   P10     P11
>       byte 6:   P12     P13
>       byte 7:   P14     P15
> 
>   4 bpp (LSB first):
> 
>               bits7-4 bits3-0
>               ------- -------
>       byte 0:    P1      P0
>       byte 1:    P3      P2
>       byte 2:    P5      P4
>       byte 3:    P7      P6
>       byte 4:    P9      P8
>       byte 5:   P11     P10
>       byte 6:   P13     P12
>       byte 7:   P15     P14

I think I can guess what you meant there, and it looks understandable
to me. These tables are actually very clear, and leave only one thing
undefined: when multiple bits form a pixel, in which order do the bits
form the value. I recall you said fbdev allows for both orderings but
only one order is ever used if I understood right.

> > Also, when drm_fourcc.h is describing pixel formats, it needs to
> > consider only how a little-endian CPU accesses them. That's how pixel
> > data in memory is described. Display hardware plays no part in that.
> > It is the driver's job to expose the pixel formats that match display
> > hardware behaviour.  
> 
> But if the "CPU format" does not match the "display support",
> all pixel data must be converted?

Of course. If the driver author does not want to convert pixel data in
flight, then the author should not let the driver expose a format that
needs conversion.


Thanks,
pq

Geert Uytterhoeven March 15, 2022, 8:57 a.m. UTC | #11

Hi Pekka,

On Tue, Mar 15, 2022 at 9:46 AM Pekka Paalanen <[e-mail]> wrote:
> On Tue, 15 Mar 2022 08:51:31 +0100
> Geert Uytterhoeven <[e-mail]> wrote:
> > On Tue, Mar 15, 2022 at 8:33 AM Pekka Paalanen <[e-mail]> wrote:
> > > On Tue, 15 Mar 2022 09:15:08 +1100 (AEDT)
> > > Finn Thain <[e-mail]> wrote:
> > > > On Mon, 14 Mar 2022, Geert Uytterhoeven wrote:
> > > > > On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:
> > > > > > On Mon, 14 Mar 2022 14:30:18 +0100
> > > > > > Geert Uytterhoeven <[e-mail]> wrote:
> > > > > > > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:
> > > > > > > > Introduce fourcc codes for color-indexed frame buffer formats with
> > > > > > > > two, four, and sixteen colors, and provide a mapping from bit per
> > > > > > > > pixel and depth to fourcc codes.
> > > > > > > >
> > > > > > > > As the number of bits per pixel is less than eight, these rely on
> > > > > > > > proper block handling for the calculation of bits per pixel and
> > > > > > > > pitch.
> > > > > > > >
> > > > > > > > Signed-off-by: Geert Uytterhoeven <[e-mail]>
> > > > > > >
> > > > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > > > @@ -99,7 +99,10 @@ extern "C" {
> > > > > > > >  #define DRM_FORMAT_INVALID     0
> > > > > > > >
> > > > > > > >  /* color index */
> > > > > > > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > > > > > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > > > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > > > > > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > > > > > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > > > > > > >
> > > > > > > >  /* 8 bpp Red */
> > > > > > > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
> > > > > > >
> > > > > > > After replying to Ilia's comment[1], I realized the CFB drawing
> > > > > > > operations use native byte and bit ordering, unless
> > > > > > > FBINFO_FOREIGN_ENDIAN is set.
> > > > > > > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > > > > > > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > > > > > > (sh7760fb configures ordering to match host order).
> > > > > > > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > > > > > > guess they are broken on big-endian.
> > > > > > > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > > > > > > on little-endian.
> > > > > > >
> > > > > > > Hence the above should become:
> > > > > > >
> > > > > > >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > > > > > > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > > >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > > > > > > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> > > > > > >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > > > > > > [7:0] C1:C0 4:4 two pixels/byte */
> > > > > > >
> > > > > > > The same changes should be made for DRM_FORMAT_[RD][124].
> > > > > > >
> > > > > > > The fbdev emulation code should gain support for these with and without
> > > > > > > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> > > > > > >
> > > > > > > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > > > > > > [2] See p.30 of the VIDC datasheet
> > > > > > >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > > > > > > [3] See p.1178 of the SH7660 datasheet
> > > > > > >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf
> > > > > >
> > > > > > why would CPU endianess affect the order of bits in a byte?
> > > > >
> > > > > It doesn't, but see below.
> > > > >
> > > > > > Do you mean that bit 0 one machine is (1 << 0), and on another machine
> > > > > > bit 0 is (1 << 7)?
> > > > >
> > > > > No, I mean that in case of multiple pixels per byte, the display
> > > > > hardware pumps out pixels to the CRTC starting from either the MSB
> > > > > or the LSB of the first display byte.  Which order depends on the
> > > > > display hardware, not on the CPU.
> > > > >
> > > > > > In C, we have only one way to address bits of a byte and that is with
> > > > > > arithmetic. You cannot take the address of a bit any other way, can you?
> > > > > >
> > > > > > Can we standardise on "bit n of a byte is addressed as (1 << n)"?
> > > > >
> > > > > BIT(n) in Linux works the same for little- and big-endian CPUs.
> > > > > But display hardware may use a different bit order.
> > > >
> > > > Perhaps some of this confusion could be avoided if you describe the
> > > > problem in terms of the sequence of scan-out of pixels, rather than in
> > > > terms of the serialization of bits. The significance of bits within each
> > > > pixel and the ordering of pixels within each memory word are independent,
> > > > right?
> > >
> > > Yes, that might help.
> >
> > Display:
> >
> >      P0  P1  P2  P3  P4  P5  P6  P7  P8  P9 P10 P11 P12 P13 P14 P15
> >
> >     P15 P14 P13 P12 P11 P10  P9  P8  P7  P6  P5  P4  P3  P2  P1  P0
>
> Hi Geert,
>
> does this mean the display hardware emits even rows from left to right
> and odd rows from right to left?

No, it means I should have my morning coffee first, and remove all
temporary cruft before pressing send :-(

The above paragraph should have read:

    Display (16 pixels):

        P0  P1  P2  P3  P4  P5  P6  P7  P8  P9 P10 P11 P12 P13 P14 P15

> I'm guessing P stands for "pixel".

Exactly.

> > Memory:
> >
> >   1 bpp (MSB first):
> >
> >               bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
> >               ---- ---- ---- ---- ---- ---- ---- ----
> >       byte 0:   P0   P1   P2   P3   P4   P5   P6   P7
> >       byte 1:   P8   P9  P10  P11  P12  P13  P14  P15
> >
> >   1 bpp (LSB first):
> >
> >               bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
> >               ---- ---- ---- ---- ---- ---- ---- ----
> >       byte 0:   P7   P6   P5   P4   P3   P2   P1   P0
> >       byte 1:  P15  P14  P13  P12  P11  P10   P9   P8
> >
> >   2 bpp (MSB first):
> >
> >               bits7-6 bits5-4 bits3-2 bits1-0
> >               ------- ------- ------- -------
> >       byte 0:    P0      P1      P2      P3
> >       byte 1:    P4      P5      P6      P7
> >       byte 2:    P8      P9     P10     P11
> >       byte 3:   P12     P13     P14     P15
> >
> >   2 bpp (LSB first):
> >
> >               bits7-6 bits5-4 bits3-2 bits1-0
> >               ------- ------- ------- -------
> >       byte 0:    P3      P2      P1      P0
> >       byte 1:    P7      P6      P5      P4
> >       byte 2:   P11     P10      P9      P8
> >       byte 3:   P15     P14     P13     P12
> >
> >   4 bpp (MSB first):
> >
> >               bits7-4 bits3-0
> >               ------- -------
> >       byte 0:    P0      P1
> >       byte 1:    P2      P3
> >       byte 2:    P4      P5
> >       byte 3:    P6      P7
> >       byte 4:    P8      P9
> >       byte 5:   P10     P11
> >       byte 6:   P12     P13
> >       byte 7:   P14     P15
> >
> >   4 bpp (LSB first):
> >
> >               bits7-4 bits3-0
> >               ------- -------
> >       byte 0:    P1      P0
> >       byte 1:    P3      P2
> >       byte 2:    P5      P4
> >       byte 3:    P7      P6
> >       byte 4:    P9      P8
> >       byte 5:   P11     P10
> >       byte 6:   P13     P12
> >       byte 7:   P15     P14
>
> I think I can guess what you meant there, and it looks understandable
> to me. These tables are actually very clear, and leave only one thing
> undefined: when multiple bits form a pixel, in which order do the bits
> form the value. I recall you said fbdev allows for both orderings but
> only one order is ever used if I understood right.

Indeed.  The third ordering is the ordering of the bits in a pixel.
As fb_bitfield.msb_right is always false, no hardware ever supported by
fbdev used the other ordering, so we only have to care about:

   1 bpp: P = [ bitN ]
   2 bpp: P = [ bitN bitN-1 ]
   4 bpp: P = [ bitN bitN-1 bitN-2 bitN-3 ]

> > > Also, when drm_fourcc.h is describing pixel formats, it needs to
> > > consider only how a little-endian CPU accesses them. That's how pixel
> > > data in memory is described. Display hardware plays no part in that.
> > > It is the driver's job to expose the pixel formats that match display
> > > hardware behaviour.
> >
> > But if the "CPU format" does not match the "display support",
> > all pixel data must be converted?
>
> Of course. If the driver author does not want to convert pixel data in
> flight, then the author should not let the driver expose a format that
> needs conversion.

... in which case we need a DRM fourcc code for the format?

BTW, Atari and Amiga use bitplanes for bpp <= 8, so they need
conversion anyway.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Pekka Paalanen March 15, 2022, 10:48 a.m. UTC | #12

On Tue, 15 Mar 2022 09:57:23 +0100
Geert Uytterhoeven <[e-mail]> wrote:

> Hi Pekka,
> 
> On Tue, Mar 15, 2022 at 9:46 AM Pekka Paalanen <[e-mail]> wrote:
> > On Tue, 15 Mar 2022 08:51:31 +0100
> > Geert Uytterhoeven <[e-mail]> wrote:  
> > > On Tue, Mar 15, 2022 at 8:33 AM Pekka Paalanen <[e-mail]> wrote:  
> > > > On Tue, 15 Mar 2022 09:15:08 +1100 (AEDT)
> > > > Finn Thain <[e-mail]> wrote:  
> > > > > On Mon, 14 Mar 2022, Geert Uytterhoeven wrote:  
> > > > > > On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen <[e-mail]> wrote:  
> > > > > > > On Mon, 14 Mar 2022 14:30:18 +0100
> > > > > > > Geert Uytterhoeven <[e-mail]> wrote:  
> > > > > > > > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven <[e-mail]> wrote:  
> > > > > > > > > Introduce fourcc codes for color-indexed frame buffer formats with
> > > > > > > > > two, four, and sixteen colors, and provide a mapping from bit per
> > > > > > > > > pixel and depth to fourcc codes.
> > > > > > > > >
> > > > > > > > > As the number of bits per pixel is less than eight, these rely on
> > > > > > > > > proper block handling for the calculation of bits per pixel and
> > > > > > > > > pitch.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Geert Uytterhoeven <[e-mail]>  
> > > > > > > >  
> > > > > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > > > > @@ -99,7 +99,10 @@ extern "C" {
> > > > > > > > >  #define DRM_FORMAT_INVALID     0
> > > > > > > > >
> > > > > > > > >  /* color index */
> > > > > > > > > -#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
> > > > > > > > > +#define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > > > > > +#define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
> > > > > > > > > +#define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
> > > > > > > > > +#define DRM_FORMAT_C8          fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
> > > > > > > > >
> > > > > > > > >  /* 8 bpp Red */
> > > > > > > > >  #define DRM_FORMAT_R8          fourcc_code('R', '8', ' ', ' ') /* [7:0] R */  
> > > > > > > >
> > > > > > > > After replying to Ilia's comment[1], I realized the CFB drawing
> > > > > > > > operations use native byte and bit ordering, unless
> > > > > > > > FBINFO_FOREIGN_ENDIAN is set.
> > > > > > > > While Amiga, Atari, and Sun-3 use big-endian bit ordering,
> > > > > > > > e.g. Acorn VIDC[2] uses little endian, and SH7760[3] is configurable
> > > > > > > > (sh7760fb configures ordering to match host order).
> > > > > > > > BTW, ssd130{7fb,x}_update_rect() both assume little-endian, so I
> > > > > > > > guess they are broken on big-endian.
> > > > > > > > Fbtest uses big-endian bit ordering, so < 8 bpp is probably broken
> > > > > > > > on little-endian.
> > > > > > > >
> > > > > > > > Hence the above should become:
> > > > > > > >
> > > > > > > >     #define DRM_FORMAT_C1          fourcc_code('C', '1', ' ', ' ') /*
> > > > > > > > [7:0] C7:C6:C5:C4:C3:C2:C1:C0 1:1:1:1:1:1:1:1 eight pixels/byte */
> > > > > > > >     #define DRM_FORMAT_C2          fourcc_code('C', '2', ' ', ' ') /*
> > > > > > > > [7:0] C3:C2:C1:C0 2:2:2:2 four pixels/byte */
> > > > > > > >     #define DRM_FORMAT_C4          fourcc_code('C', '4', ' ', ' ') /*
> > > > > > > > [7:0] C1:C0 4:4 two pixels/byte */
> > > > > > > >
> > > > > > > > The same changes should be made for DRM_FORMAT_[RD][124].
> > > > > > > >
> > > > > > > > The fbdev emulation code should gain support for these with and without
> > > > > > > > DRM_FORMAT_BIG_ENDIAN, the latter perhaps only on big-endian platforms?
> > > > > > > >
> > > > > > > > [1] https://lore.kernel.org/r/CAKb7UvgEdm9U=[e-mail]/
> > > > > > > > [2] See p.30 of the VIDC datasheet
> > > > > > > >     http://chrisacorns.computinghistory.org.uk/docs/Acorn/Misc/Acorn_VIDC_Datasheet.pdf
> > > > > > > > [3] See p.1178 of the SH7660 datasheet
> > > > > > > >     https://datasheet.octopart.com/HD6417760BL200AV-Renesas-datasheet-14105759.pdf  
> > > > > > >
> > > > > > > why would CPU endianess affect the order of bits in a byte?  
> > > > > >
> > > > > > It doesn't, but see below.
> > > > > >  
> > > > > > > Do you mean that bit 0 one machine is (1 << 0), and on another machine
> > > > > > > bit 0 is (1 << 7)?  
> > > > > >
> > > > > > No, I mean that in case of multiple pixels per byte, the display
> > > > > > hardware pumps out pixels to the CRTC starting from either the MSB
> > > > > > or the LSB of the first display byte.  Which order depends on the
> > > > > > display hardware, not on the CPU.
> > > > > >  
> > > > > > > In C, we have only one way to address bits of a byte and that is with
> > > > > > > arithmetic. You cannot take the address of a bit any other way, can you?
> > > > > > >
> > > > > > > Can we standardise on "bit n of a byte is addressed as (1 << n)"?  
> > > > > >
> > > > > > BIT(n) in Linux works the same for little- and big-endian CPUs.
> > > > > > But display hardware may use a different bit order.  
> > > > >
> > > > > Perhaps some of this confusion could be avoided if you describe the
> > > > > problem in terms of the sequence of scan-out of pixels, rather than in
> > > > > terms of the serialization of bits. The significance of bits within each
> > > > > pixel and the ordering of pixels within each memory word are independent,
> > > > > right?  
> > > >
> > > > Yes, that might help.  
> > >
> > > Display:
> > >
> > >      P0  P1  P2  P3  P4  P5  P6  P7  P8  P9 P10 P11 P12 P13 P14 P15
> > >
> > >     P15 P14 P13 P12 P11 P10  P9  P8  P7  P6  P5  P4  P3  P2  P1  P0  
> >
> > Hi Geert,
> >
> > does this mean the display hardware emits even rows from left to right
> > and odd rows from right to left?  
> 
> No, it means I should have my morning coffee first, and remove all
> temporary cruft before pressing send :-(
> 
> The above paragraph should have read:
> 
>     Display (16 pixels):
> 
>         P0  P1  P2  P3  P4  P5  P6  P7  P8  P9 P10 P11 P12 P13 P14 P15
> 
> > I'm guessing P stands for "pixel".  
> 
> Exactly.
> 
> > > Memory:
> > >
> > >   1 bpp (MSB first):
> > >
> > >               bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
> > >               ---- ---- ---- ---- ---- ---- ---- ----
> > >       byte 0:   P0   P1   P2   P3   P4   P5   P6   P7
> > >       byte 1:   P8   P9  P10  P11  P12  P13  P14  P15
> > >
> > >   1 bpp (LSB first):
> > >
> > >               bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
> > >               ---- ---- ---- ---- ---- ---- ---- ----
> > >       byte 0:   P7   P6   P5   P4   P3   P2   P1   P0
> > >       byte 1:  P15  P14  P13  P12  P11  P10   P9   P8
> > >
> > >   2 bpp (MSB first):
> > >
> > >               bits7-6 bits5-4 bits3-2 bits1-0
> > >               ------- ------- ------- -------
> > >       byte 0:    P0      P1      P2      P3
> > >       byte 1:    P4      P5      P6      P7
> > >       byte 2:    P8      P9     P10     P11
> > >       byte 3:   P12     P13     P14     P15
> > >
> > >   2 bpp (LSB first):
> > >
> > >               bits7-6 bits5-4 bits3-2 bits1-0
> > >               ------- ------- ------- -------
> > >       byte 0:    P3      P2      P1      P0
> > >       byte 1:    P7      P6      P5      P4
> > >       byte 2:   P11     P10      P9      P8
> > >       byte 3:   P15     P14     P13     P12
> > >
> > >   4 bpp (MSB first):
> > >
> > >               bits7-4 bits3-0
> > >               ------- -------
> > >       byte 0:    P0      P1
> > >       byte 1:    P2      P3
> > >       byte 2:    P4      P5
> > >       byte 3:    P6      P7
> > >       byte 4:    P8      P9
> > >       byte 5:   P10     P11
> > >       byte 6:   P12     P13
> > >       byte 7:   P14     P15
> > >
> > >   4 bpp (LSB first):
> > >
> > >               bits7-4 bits3-0
> > >               ------- -------
> > >       byte 0:    P1      P0
> > >       byte 1:    P3      P2
> > >       byte 2:    P5      P4
> > >       byte 3:    P7      P6
> > >       byte 4:    P9      P8
> > >       byte 5:   P11     P10
> > >       byte 6:   P13     P12
> > >       byte 7:   P15     P14  
> >
> > I think I can guess what you meant there, and it looks understandable
> > to me. These tables are actually very clear, and leave only one thing
> > undefined: when multiple bits form a pixel, in which order do the bits
> > form the value. I recall you said fbdev allows for both orderings but
> > only one order is ever used if I understood right.  
> 
> Indeed.  The third ordering is the ordering of the bits in a pixel.
> As fb_bitfield.msb_right is always false, no hardware ever supported by
> fbdev used the other ordering, so we only have to care about:
> 
>    1 bpp: P = [ bitN ]
>    2 bpp: P = [ bitN bitN-1 ]
>    4 bpp: P = [ bitN bitN-1 bitN-2 bitN-3 ]

Excellent!

> > > > Also, when drm_fourcc.h is describing pixel formats, it needs to
> > > > consider only how a little-endian CPU accesses them. That's how pixel
> > > > data in memory is described. Display hardware plays no part in that.
> > > > It is the driver's job to expose the pixel formats that match display
> > > > hardware behaviour.  
> > >
> > > But if the "CPU format" does not match the "display support",
> > > all pixel data must be converted?  
> >
> > Of course. If the driver author does not want to convert pixel data in
> > flight, then the author should not let the driver expose a format that
> > needs conversion.  
> 
> ... in which case we need a DRM fourcc code for the format?

Yes. You can define any new formats you need as long as the format
definition does not depend on (is not affected/modified by) CPU
endianess or any other CPU or display hardware property. I believe this
is the convention used with drm_fourcc.

If the format wanted by display hardware depends on something, then you
need all relevant pixel formats defined and choose at build or driver
initialisation time which ones to expose.

> BTW, Atari and Amiga use bitplanes for bpp <= 8, so they need
> conversion anyway.

Right, that's probably the most reasonable approach. If you really
wanted to expose bitplanes, I could imagine that some new format
modifiers could achieve that.


Thanks,
pq

Patch

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 6c76bd821d17e7c7..29f4fe199c4ddcf0 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -43,6 +43,21 @@  uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth)
 	uint32_t fmt = DRM_FORMAT_INVALID;
 
 	switch (bpp) {
+	case 1:
+		if (depth == 1)
+			fmt = DRM_FORMAT_C1;
+		break;
+
+	case 2:
+		if (depth == 2)
+			fmt = DRM_FORMAT_C2;
+		break;
+
+	case 4:
+		if (depth == 4)
+			fmt = DRM_FORMAT_C4;
+		break;
+
 	case 8:
 		if (depth == 8)
 			fmt = DRM_FORMAT_C8;
@@ -132,6 +147,12 @@  EXPORT_SYMBOL(drm_driver_legacy_fb_format);
 const struct drm_format_info *__drm_format_info(u32 format)
 {
 	static const struct drm_format_info formats[] = {
+		{ .format = DRM_FORMAT_C1,		.depth = 1,  .num_planes = 1,
+		  .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
+		{ .format = DRM_FORMAT_C2,		.depth = 2,  .num_planes = 1,
+		  .char_per_block = { 1, }, .block_w = { 4, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
+		{ .format = DRM_FORMAT_C4,		.depth = 4,  .num_planes = 1,
+		  .char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1, }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
 		{ .format = DRM_FORMAT_C8,		.depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1, .is_color_indexed = true },
 		{ .format = DRM_FORMAT_R8,		.depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
 		{ .format = DRM_FORMAT_R10,		.depth = 10, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fc0c1454d2757d5d..457ed39cc48f08e1 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -99,7 +99,10 @@  extern "C" {
 #define DRM_FORMAT_INVALID	0
 
 /* color index */
-#define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
+#define DRM_FORMAT_C1		fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
+#define DRM_FORMAT_C2		fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
+#define DRM_FORMAT_C4		fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
+#define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C 8 one pixel/byte */
 
 /* 8 bpp Red */
 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */