From patchwork Thu Jul 14 12:06:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12917806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9019CCA47B for ; Thu, 14 Jul 2022 12:07:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9292B112A1B; Thu, 14 Jul 2022 12:06:47 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26B1A1128BF; Thu, 14 Jul 2022 12:06:35 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7ABADB824E9; Thu, 14 Jul 2022 12:06:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 818D2C341D0; Thu, 14 Jul 2022 12:06:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657800390; bh=kp22WVyJ8hn3YbHi+EgLuYcggIAQWpbc8D/KBpf/UN0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n+jmakYzM3ydD4xAbxjEjIFBUOywb3gDCdCualPh0TBzt1wm8+7+i71Mt53J1ULEm 99562AtJWmf/tbk7UnAEXeeanIC3MfPB4NFPFu0+xJARb0T+rH3twHGmWO+BDfk2g4 gakimnuaqKfMZ6lv8M4KawJLsdt/dhMfDtttuXBRUaxIeZqgU6ZlcNgn3AgMMEXyF6 i+YOmPLiijUIarTXfkPiwLYdP2GdM+dnhyRZjrXmSUOLEcJsLKGA1G9qZWC04sEScH ow48AOtQfBW7Da+3cf34kdFeZupE6xu9OzNCyAeQZX/ONS97ljLNEbLrxblIcI8uA0 aeJxpP7S5kiQg== Received: from mchehab by mail.kernel.org with local (Exim 4.95) (envelope-from ) id 1oBxbw-0059tR-6p; Thu, 14 Jul 2022 13:06:28 +0100 From: Mauro Carvalho Chehab To: Subject: [PATCH v2 19/21] drm/i915/gt: document TLB cache invalidation functions Date: Thu, 14 Jul 2022 13:06:24 +0100 Message-Id: <912156cd83488daf0c600f56442245bbe36ba37f.1657800199.git.mchehab@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Chris Wilson , Rodrigo Vivi , Mauro Carvalho Chehab , intel-gfx@lists.freedesktop.org, Prathap Kumar Valsan Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a description for the kAPI functions inside intel_tlb.c. Signed-off-by: Mauro Carvalho Chehab --- To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@kernel.org/ drivers/gpu/drm/i915/gt/intel_tlb.c | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c b/drivers/gpu/drm/i915/gt/intel_tlb.c index 15ed83226676..aa2e0086ae88 100644 --- a/drivers/gpu/drm/i915/gt/intel_tlb.c +++ b/drivers/gpu/drm/i915/gt/intel_tlb.c @@ -146,6 +146,18 @@ static void mmio_invalidate_full(struct intel_gt *gt) intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL); } +/** + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation + * @gt: GT structure + * @seqno: sequence number + * + * Do a full TLB cache invalidation if the @seqno is bigger than the last + * full TLB cache invalidation. + * + * Note: + * The TLB cache invalidation logic depends on GEN-specific registers. + * It currently supports GEN8 to GEN12 and GuC-based TLB cache invalidation. + */ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno) { intel_wakeref_t wakeref; @@ -220,6 +232,17 @@ static bool mmio_invalidate_range(struct intel_gt *gt, u64 start, u64 length) return err == 0; } +/** + * intel_gt_invalidate_tlb_range - do full TLB cache invalidation + * @gt: GT structure + * @start: range start + * @length: range length + * + * Do a selected TLB cache invalidation on a range pointed by @start + * with @length size. + * + * Only some GuC-based GPUs can do a selective cache invalidation. + */ bool intel_gt_invalidate_tlb_range(struct intel_gt *gt, u64 start, u64 length) { @@ -247,12 +270,25 @@ bool intel_gt_invalidate_tlb_range(struct intel_gt *gt, return true; } +/** + * intel_gt_init_tlb - initialize TLB-specific vars + * @gt: GT structure + * + * TLB cache invalidation logic internally uses some resources that require + * initialization. Should be called before doing any TLB cache invalidation. + */ void intel_gt_init_tlb(struct intel_gt *gt) { mutex_init(>->tlb.invalidate_lock); seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock); } +/** + * intel_gt_fini_tlb - initialize TLB-specific vars + * @gt: GT structure + * + * Frees any resources needed by TLB cache invalidation logic. + */ void intel_gt_fini_tlb(struct intel_gt *gt) { mutex_destroy(>->tlb.invalidate_lock);