From patchwork Thu Aug 28 15:01:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 4805341 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1A0C79F2A9 for ; Thu, 28 Aug 2014 15:02:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 622BE2010B for ; Thu, 28 Aug 2014 15:02:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CB1942010F for ; Thu, 28 Aug 2014 15:02:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94A186E642; Thu, 28 Aug 2014 08:02:02 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qg0-f54.google.com (mail-qg0-f54.google.com [209.85.192.54]) by gabe.freedesktop.org (Postfix) with ESMTP id C96196E027; Thu, 28 Aug 2014 08:02:00 -0700 (PDT) Received: by mail-qg0-f54.google.com with SMTP id q107so842380qgd.41 for ; Thu, 28 Aug 2014 08:02:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=TVF35vf06uB7mgKX/3I1nKMgz+oiu/zsb4oLnWMr1d4=; b=OwnEPNNodlMgRlsDTi3FmSYo3WXhthzkK6x/iozwvOzLXUdz8vrnLTYXHXLDQAcwYP mnA3T1G9R6JZsuiV0WPuFp0Yoc57jpMG+ks+MrpVEjV1/7btTxSjEZBOOO7TBcaBT/wv 6yEuZpCi2r4iW0qjYH3QOVzIsbSKhiaSFTSKVsh9bkpkFz4NduQjT28EC9CSuuRxis2D +43jJE500QKpOBoXirR6HHXFBxRwy9kPjhwzPgUiA49d6PAwB2YGcSm3+GQHyNGsbgUN sAKCElJveFtZNrvf9Mq9EIdgXgCwWhuQENs+QztUpYB0wVrgExnp0Lu5euPT/JHMxY1r /VyA== MIME-Version: 1.0 X-Received: by 10.140.101.86 with SMTP id t80mr6778443qge.91.1409238120156; Thu, 28 Aug 2014 08:02:00 -0700 (PDT) Received: by 10.140.94.75 with HTTP; Thu, 28 Aug 2014 08:01:59 -0700 (PDT) In-Reply-To: <53FEEEF4.7030401@vodafone.de> References: <1409208961-7322-1-git-send-email-michel@daenzer.net> <53FEEEF4.7030401@vodafone.de> Date: Thu, 28 Aug 2014 11:01:59 -0400 Message-ID: Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Add RADEON_GEM_CPU_ACCESS BO creation flag From: Alex Deucher To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: "mesa-dev@lists.freedesktop.org" , =?UTF-8?Q?Michel_D=C3=A4nzer?= , Maling list - DRI developers X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Aug 28, 2014 at 4:57 AM, Christian König wrote: > Am 28.08.2014 um 08:56 schrieb Michel Dänzer: > >> From: Michel Dänzer >> >> This flag is a hint that userspace expects the BO to be accessed by the >> CPU. We can use that hint to prevent such BOs from ever being stored in >> the CPU inaccessible part of VRAM. >> >> Signed-off-by: Michel Dänzer > > > This patch is Reviewed-by: Christian König Applied to my -next tree. > > I think we need a similar negative flags as well, e.g. > RADEON_GEM_NO_CPU_ACCESS. > > This way we can stop forcing buffers into the visible VRAM while pinning > them for scanout. How about the attached patch? Alex > > Regards, > Christian. > > >> --- >> drivers/gpu/drm/radeon/radeon_object.c | 11 +++++++++-- >> include/uapi/drm/radeon_drm.h | 2 ++ >> 2 files changed, 11 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/radeon/radeon_object.c >> b/drivers/gpu/drm/radeon/radeon_object.c >> index dc74cc5..908ea541 100644 >> --- a/drivers/gpu/drm/radeon/radeon_object.c >> +++ b/drivers/gpu/drm/radeon/radeon_object.c >> @@ -143,7 +143,12 @@ void radeon_ttm_placement_from_domain(struct >> radeon_bo *rbo, u32 domain) >> for (i = 0; i < c; ++i) { >> rbo->placements[i].fpfn = 0; >> - rbo->placements[i].lpfn = 0; >> + if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && >> + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) >> + rbo->placements[i].lpfn = >> + rbo->rdev->mc.visible_vram_size >> >> PAGE_SHIFT; >> + else >> + rbo->placements[i].lpfn = 0; >> } >> /* >> @@ -151,7 +156,9 @@ void radeon_ttm_placement_from_domain(struct radeon_bo >> *rbo, u32 domain) >> * improve fragmentation quality. >> * 512kb was measured as the most optimal number. >> */ >> - if (rbo->tbo.mem.size > 512 * 1024) { >> + if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) && >> + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) && >> + rbo->tbo.mem.size > 512 * 1024) { >> for (i = 0; i < c; i++) { >> rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; >> } >> diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h >> index 509b2d7..bf0067b 100644 >> --- a/include/uapi/drm/radeon_drm.h >> +++ b/include/uapi/drm/radeon_drm.h >> @@ -799,6 +799,8 @@ struct drm_radeon_gem_info { >> #define RADEON_GEM_NO_BACKING_STORE (1 << 0) >> #define RADEON_GEM_GTT_UC (1 << 1) >> #define RADEON_GEM_GTT_WC (1 << 2) >> +/* BO is expected to be accessed by the CPU */ >> +#define RADEON_GEM_CPU_ACCESS (1 << 3) >> struct drm_radeon_gem_create { >> uint64_t size; > > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev From d6a65c62241fe2b3c1a0dd799f2af0802297446c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 28 Aug 2014 10:59:05 -0400 Subject: [PATCH] drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag Allows pinning of buffers in the non-CPU visible portion of vram. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_object.c | 10 +++++++--- include/uapi/drm/radeon_drm.h | 2 ++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 09b039a..b71e8e0 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -314,10 +314,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, unsigned lpfn = 0; /* force to pin into visible video ram */ - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) - lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; - else + if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) { + if (bo->flags & RADEON_GEM_NO_CPU_ACCESS) + lpfn = bo->rdev->mc.real_vram_size >> PAGE_SHIFT; + else + lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + } else { lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */ + } if (max_offset) lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT)); diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index f755f20..d2346fd 100644 --- a/include/uapi/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h @@ -803,6 +803,8 @@ struct drm_radeon_gem_info { #define RADEON_GEM_GTT_WC (1 << 2) /* BO is expected to be accessed by the CPU */ #define RADEON_GEM_CPU_ACCESS (1 << 3) +/* BO is expected to not be accessed by the CPU */ +#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) struct drm_radeon_gem_create { uint64_t size; -- 1.8.3.1