diff mbox

[1/3] drm/radeon: take exclusive_lock in read mode during ring tests

Message ID CADnq5_NQgMPJ1iwSE2bCeOyGEZqcG94dCcteBh=fHyHvibTwjQ@mail.gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Alex Deucher Aug. 18, 2014, 8:56 p.m. UTC
On Mon, Aug 18, 2014 at 4:02 PM, Maarten Lankhorst
<maarten.lankhorst@canonical.com> wrote:
> Hey,
>
> On 18-08-14 18:10, Alex Deucher wrote:
>> On Mon, Aug 18, 2014 at 12:07 PM, Christian König
>> <deathsimple@vodafone.de> wrote:
>>>> Yeah, looks like a bug.  I think the attached patch should fix it.
>>>
>>> Sounds logical and the patch is Reviewed-by: Christian König
>>> <christian.koenig@amd.com>
>>>
>>> Going to apply Maartens patch on top and test that one a bit to make sure it
>>> works as expected.
>>
>> pushed my current -fixes queue to my drm-fixes-3.17-wip branch if that helps.
>
> Thanks, maybe that fixes uvd on resume for me. :-)
>
> I'll have to rework it to include the changes, but does resuming everything in the order of my v2 patch look sane?
> Then as a final act I'm downgrading to read, and run the tests.

Seems sane.  Looks like we probably also need this attached patch as
well to be on the safe side for displays.  It would be nice to unify
the suspend/resume and gpu_reset paths at some point.

Alex
diff mbox

Patch

From e8cfbe410871de7a4805f13c6f18c3551741c639 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 18 Aug 2014 16:51:46 -0400
Subject: [PATCH] drm/radeon: fix display handling in radeon_gpu_reset

If the display hw was reset or a hard reset was used,
we need to re-init some of the common display hardware as well.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/radeon/radeon_device.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 8e61870..6a219bc 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1681,6 +1681,7 @@  int radeon_gpu_reset(struct radeon_device *rdev)
 	/* block TTM */
 	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 	radeon_suspend(rdev);
+	radeon_hpd_fini(rdev);
 
 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 		ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
@@ -1737,6 +1738,21 @@  retry:
 		radeon_pm_resume(rdev);
 	}
 
+	/* init dig PHYs, disp eng pll */
+	if (rdev->is_atom_bios) {
+		radeon_atom_encoder_init(rdev);
+		radeon_atom_disp_eng_pll_init(rdev);
+		/* turn on the BL */
+		if (rdev->mode_info.bl_encoder) {
+			u8 bl_level = radeon_get_backlight_level(rdev,
+								 rdev->mode_info.bl_encoder);
+			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
+						   bl_level);
+		}
+	}
+	/* reset hpd state */
+	radeon_hpd_init(rdev);
+
 	drm_helper_resume_force_mode(rdev->ddev);
 
 	/* set the power state here in case we are a PX system or headless */
-- 
1.8.3.1