From patchwork Tue Feb 10 15:19:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 5807901 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 527589F36A for ; Tue, 10 Feb 2015 15:19:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4058E2011E for ; Tue, 10 Feb 2015 15:19:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D0E8A20117 for ; Tue, 10 Feb 2015 15:19:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5ADDD6E228; Tue, 10 Feb 2015 07:19:32 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qg0-f46.google.com (mail-qg0-f46.google.com [209.85.192.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 797836E228 for ; Tue, 10 Feb 2015 07:19:31 -0800 (PST) Received: by mail-qg0-f46.google.com with SMTP id z107so13189939qgd.5 for ; Tue, 10 Feb 2015 07:19:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=nYUhZhL96fJhPcyLhinEry+mXxcXsa4YHeDFRb7jG9A=; b=wqfT0u7coj3N/ugm7H1hpLVX2ADJNM/5UxgcS4KZF6sNeW+6RBQDX5IzsVXz00eHX7 m73zWMY3wtpFAs1OFkVmPCXNzOhXP7pt1Gx90VnapX8+ZsSExF8M4ZgychUU1q8MTGx+ /5Csc5AsE3KkWxVx189HjduJj1T121pNw0U1uqQc0eInvfVsEshc52Zzd3NGW6qxNXV5 5gDt/gAbUi5AmZmVfLxc+PwiRf9WzR4W/sj4yNJAr3ZWs7OVD3rxa5IYNAnBR78OnxnT GUqriVTWbxU9r/V2NpK5EIQX28mRr1Qk7SIHtoPnLISGS6AtR3/mq4N6cLb2LTYt62Kw dgHQ== MIME-Version: 1.0 X-Received: by 10.224.79.82 with SMTP id o18mr39175362qak.3.1423581570788; Tue, 10 Feb 2015 07:19:30 -0800 (PST) Received: by 10.140.41.104 with HTTP; Tue, 10 Feb 2015 07:19:30 -0800 (PST) In-Reply-To: <1423574800-29627-2-git-send-email-deathsimple@vodafone.de> References: <1423574800-29627-1-git-send-email-deathsimple@vodafone.de> <1423574800-29627-2-git-send-email-deathsimple@vodafone.de> Date: Tue, 10 Feb 2015 10:19:30 -0500 Message-ID: Subject: Re: [PATCH 2/2] drm/radeon: only enable kv/kb dpm interrupts once v2 From: Alex Deucher To: =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: Maling list - DRI developers X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, Feb 10, 2015 at 8:26 AM, Christian König wrote: > From: Alex Deucher > > Enable at init and disable on fini. Workaround for hardware problems. > > v2 (chk): extend commit message > > Signed-off-by: Alex Deucher > Signed-off-by: Christian König > Cc: stable@vger.kernel.org Applied a slightly modified version of this. Alex > --- > drivers/gpu/drm/radeon/cik.c | 21 --------------------- > drivers/gpu/drm/radeon/kv_dpm.c | 12 ++++++++++-- > 2 files changed, 10 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 5594416..e6a4ba2 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -7373,7 +7373,6 @@ int cik_irq_set(struct radeon_device *rdev) > u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; > u32 grbm_int_cntl = 0; > u32 dma_cntl, dma_cntl1; > - u32 thermal_int; > > if (!rdev->irq.installed) { > WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); > @@ -7403,13 +7402,6 @@ int cik_irq_set(struct radeon_device *rdev) > > cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; > > - if (rdev->flags & RADEON_IS_IGP) > - thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & > - ~(THERM_INTH_MASK | THERM_INTL_MASK); > - else > - thermal_int = RREG32_SMC(CG_THERMAL_INT) & > - ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); > - > /* enable CP interrupts on all rings */ > if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { > DRM_DEBUG("cik_irq_set: sw int gfx\n"); > @@ -7513,14 +7505,6 @@ int cik_irq_set(struct radeon_device *rdev) > hpd6 |= DC_HPDx_INT_EN; > } > > - if (rdev->irq.dpm_thermal) { > - DRM_DEBUG("dpm thermal\n"); > - if (rdev->flags & RADEON_IS_IGP) > - thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; > - else > - thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; > - } > - > WREG32(CP_INT_CNTL_RING0, cp_int_cntl); > > WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); > @@ -7567,11 +7551,6 @@ int cik_irq_set(struct radeon_device *rdev) > WREG32(DC_HPD5_INT_CONTROL, hpd5); > WREG32(DC_HPD6_INT_CONTROL, hpd6); > > - if (rdev->flags & RADEON_IS_IGP) > - WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); > - else > - WREG32_SMC(CG_THERMAL_INT, thermal_int); > - > return 0; > } > > diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c > index c5eb286..d316758 100644 > --- a/drivers/gpu/drm/radeon/kv_dpm.c > +++ b/drivers/gpu/drm/radeon/kv_dpm.c > @@ -1272,6 +1272,7 @@ int kv_dpm_enable(struct radeon_device *rdev) > int kv_dpm_late_enable(struct radeon_device *rdev) > { > int ret = 0; > + u32 thermal_int; > > if (rdev->irq.installed && > r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { > @@ -1280,8 +1281,9 @@ int kv_dpm_late_enable(struct radeon_device *rdev) > DRM_ERROR("kv_set_thermal_temperature_range failed\n"); > return ret; > } > - rdev->irq.dpm_thermal = true; > - radeon_irq_set(rdev); > + thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); > + thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; > + WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); > } > > /* powerdown unused blocks for now */ > @@ -1295,6 +1297,8 @@ int kv_dpm_late_enable(struct radeon_device *rdev) > > void kv_dpm_disable(struct radeon_device *rdev) > { > + u32 thermal_int; > + > kv_smc_bapm_enable(rdev, false); > > if (rdev->family == CHIP_MULLINS) > @@ -1313,6 +1317,10 @@ void kv_dpm_disable(struct radeon_device *rdev) > kv_enable_ulv(rdev, false); > kv_reset_am(rdev); > > + thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & > + ~(THERM_INTH_MASK | THERM_INTL_MASK); > + WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); > + > kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); > } > > -- > 1.9.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel From d8aacdd4bdd2de137273699c1509643d937d5fb9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 6 Feb 2015 12:53:27 -0500 Subject: [PATCH] drm/radeon: only enable kv/kb dpm interrupts once v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable at init and disable on fini. Workaround for hardware problems. v2 (chk): extend commit message v3: add new function Signed-off-by: Alex Deucher Signed-off-by: Christian König (v2) Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/cik.c | 21 --------------------- drivers/gpu/drm/radeon/kv_dpm.c | 17 +++++++++++++++-- 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 5594416..e6a4ba2 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -7373,7 +7373,6 @@ int cik_irq_set(struct radeon_device *rdev) u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; u32 grbm_int_cntl = 0; u32 dma_cntl, dma_cntl1; - u32 thermal_int; if (!rdev->irq.installed) { WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); @@ -7403,13 +7402,6 @@ int cik_irq_set(struct radeon_device *rdev) cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; - if (rdev->flags & RADEON_IS_IGP) - thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & - ~(THERM_INTH_MASK | THERM_INTL_MASK); - else - thermal_int = RREG32_SMC(CG_THERMAL_INT) & - ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); - /* enable CP interrupts on all rings */ if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { DRM_DEBUG("cik_irq_set: sw int gfx\n"); @@ -7513,14 +7505,6 @@ int cik_irq_set(struct radeon_device *rdev) hpd6 |= DC_HPDx_INT_EN; } - if (rdev->irq.dpm_thermal) { - DRM_DEBUG("dpm thermal\n"); - if (rdev->flags & RADEON_IS_IGP) - thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; - else - thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; - } - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); @@ -7567,11 +7551,6 @@ int cik_irq_set(struct radeon_device *rdev) WREG32(DC_HPD5_INT_CONTROL, hpd5); WREG32(DC_HPD6_INT_CONTROL, hpd6); - if (rdev->flags & RADEON_IS_IGP) - WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); - else - WREG32_SMC(CG_THERMAL_INT, thermal_int); - return 0; } diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c index c5eb286..0e236d0 100644 --- a/drivers/gpu/drm/radeon/kv_dpm.c +++ b/drivers/gpu/drm/radeon/kv_dpm.c @@ -1169,6 +1169,19 @@ void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable) } } +static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable) +{ + u32 thermal_int; + + thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); + if (enable) + thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; + else + thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK); + WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); + +} + int kv_dpm_enable(struct radeon_device *rdev) { struct kv_power_info *pi = kv_get_pi(rdev); @@ -1280,8 +1293,7 @@ int kv_dpm_late_enable(struct radeon_device *rdev) DRM_ERROR("kv_set_thermal_temperature_range failed\n"); return ret; } - rdev->irq.dpm_thermal = true; - radeon_irq_set(rdev); + kv_enable_thermal_int(rdev, true); } /* powerdown unused blocks for now */ @@ -1312,6 +1324,7 @@ void kv_dpm_disable(struct radeon_device *rdev) kv_stop_dpm(rdev); kv_enable_ulv(rdev, false); kv_reset_am(rdev); + kv_enable_thermal_int(rdev, false); kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); } -- 1.8.3.1