From patchwork Thu May 5 14:22:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 9024891 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2E7AB9F372 for ; Thu, 5 May 2016 14:22:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 26B21203B4 for ; Thu, 5 May 2016 14:22:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 20D0620259 for ; Thu, 5 May 2016 14:22:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3718B6E9C6; Thu, 5 May 2016 14:22:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-yw0-x22c.google.com (mail-yw0-x22c.google.com [IPv6:2607:f8b0:4002:c05::22c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63BFB6E9C6 for ; Thu, 5 May 2016 14:22:41 +0000 (UTC) Received: by mail-yw0-x22c.google.com with SMTP id j74so124223962ywg.1 for ; Thu, 05 May 2016 07:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc; bh=YAb1tJiyLW4mW9t4qKE2+kR9aGTFqxmfMTEn+QAOSHY=; b=kNuglQH7DuTbGnV8lg2QaWcuzUzzHxHZkDtVK55OWeqPDRRtMlKQ+BXO8ulwPYt07T hzn62Mio4Od53d/s+a3DQheBpavtzqD/S0gwW3JVcgYcOMV4jnVG0/OnL2E3vt/fZ2Gq Es0e6rfmtSlJtjrnaZtQqWrZ798MYW/glAaLefl5o3OS8N41+2KJ/aZM4ZLnsOvUk7sW grCGKmyUZ+V22mH90shyfCqEoAaehEr4Oe2JCtMSK0IxygdfPsJtj1P3DtCDyKn/yBxf q6vZ7Kl2JHJZnp16vqYhWlM44QQs847xWyM6hSXGnvBY7f138wWRRNKDk98/DqhS80gg QVVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc; bh=YAb1tJiyLW4mW9t4qKE2+kR9aGTFqxmfMTEn+QAOSHY=; b=SXD1C8Xt5cXi6Vr7BuN1y42JuQnMNRmO0prnt3rkGgheqYVYKykbJmAU+muVWG9aYE wbRsoifKQghhGyvM/wRcSm+zEljUNWmEF8wpzCssCxX0iRHzLRblOyVEk5fSeQIte7ul AkGC4wxodZn1QmET38q3jhrIQt0gQ22LRK8RX2SDvDsN92JkTOowqmObR/rR2ts5N2/f tJY35bx2ZtWg54PzPGJezg002yyXix/R/LJuzdnv3qIMndqSxzZXE242d84oFwVTWBJx JoyctJDJuhpxDWW+37ZMAg2TlHRlITOAaYTNhGQEFNDGtcLsBM4+6al+kLjj5HJ134qt JELQ== X-Gm-Message-State: AOPr4FXWPKqeMZBsbAuHkyoDOMJhCjWD79Knl7ulBKZxzbRZqDBKDHyxiJ56Vsp9+ytG0iXeWJICXEL8yFHeoQ== MIME-Version: 1.0 X-Received: by 10.13.222.132 with SMTP id h126mr8299332ywe.104.1462458160531; Thu, 05 May 2016 07:22:40 -0700 (PDT) Received: by 10.37.92.85 with HTTP; Thu, 5 May 2016 07:22:40 -0700 (PDT) In-Reply-To: <1462438945-13995-1-git-send-email-dev@lynxeye.de> References: <1462438945-13995-1-git-send-email-dev@lynxeye.de> Date: Thu, 5 May 2016 10:22:40 -0400 Message-ID: Subject: Re: [PATCH] drm/radeon: fix PLL sharing on DCE6.1 From: Alex Deucher To: Lucas Stach Cc: Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , Maling list - DRI developers X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, May 5, 2016 at 5:02 AM, Lucas Stach wrote: > On DCE6.1 PPLL2 is exclusively available to UNIPHYA, so it should not > be taken into consideration when looking for an already enabled PLL > to be shared with other outputs. > > This fixes the broken VGA port (TRAVIS DP->VGA bridge) on my Richland > based laptop, where the internal display is connected to UNIPHYA through > a TRAVIS DP->LVDS bridge. > > Bug: > https://bugs.freedesktop.org/show_bug.cgi?id=78987 > > Signed-off-by: Lucas Stach Nice catch. Need to add a check for the non-dp case as well I think. How about the attached patch? Alex > --- > drivers/gpu/drm/radeon/atombios_crtc.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c > index b80b08f..401bcbd 100644 > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > @@ -1739,7 +1739,8 @@ static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) > * also in DP mode. For DP, a single PPLL can be used for all DP > * crtcs/encoders. > */ > -static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) > +static int radeon_get_shared_dp_ppll(struct radeon_device *rdev, > + struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct drm_crtc *test_crtc; > @@ -1751,6 +1752,10 @@ static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) > test_radeon_crtc = to_radeon_crtc(test_crtc); > if (test_radeon_crtc->encoder && > ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { > + /* PPLL2 is exclusive to UNIPHYA on DCE61 */ > + if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && > + test_radeon_crtc->pll_id == ATOM_PPLL2) > + continue; > /* for DP use the same PLL for all */ > if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) > return test_radeon_crtc->pll_id; > @@ -1859,7 +1864,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) > return ATOM_PPLL_INVALID; > else { > /* use the same PPLL for all DP monitors */ > - pll = radeon_get_shared_dp_ppll(crtc); > + pll = radeon_get_shared_dp_ppll(rdev, crtc); > if (pll != ATOM_PPLL_INVALID) > return pll; > } > @@ -1907,7 +1912,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) > return ATOM_PPLL_INVALID; > else { > /* use the same PPLL for all DP monitors */ > - pll = radeon_get_shared_dp_ppll(crtc); > + pll = radeon_get_shared_dp_ppll(rdev, crtc); > if (pll != ATOM_PPLL_INVALID) > return pll; > } > @@ -1962,7 +1967,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) > return ATOM_DCPLL; > else { > /* use the same PPLL for all DP monitors */ > - pll = radeon_get_shared_dp_ppll(crtc); > + pll = radeon_get_shared_dp_ppll(rdev, crtc); > if (pll != ATOM_PPLL_INVALID) > return pll; > } > -- > 2.5.5 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From 4741c95faa1c26b0f623b27f1b63b9f55e53b98b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 5 May 2016 10:16:44 -0400 Subject: [PATCH] drm/radeon: fix PLL sharing on DCE6.1 (v2) On DCE6.1 PPLL2 is exclusively available to UNIPHYA, so it should not be taken into consideration when looking for an already enabled PLL to be shared with other outputs. This fixes the broken VGA port (TRAVIS DP->VGA bridge) on my Richland based laptop, where the internal display is connected to UNIPHYA through a TRAVIS DP->LVDS bridge. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=78987 v2: agd: add check in radeon_get_shared_nondp_ppll as well, drop extra parameter. Signed-off-by: Lucas Stach Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/atombios_crtc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index bdc7b9e..2e216e2 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1740,6 +1740,7 @@ static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; struct drm_crtc *test_crtc; struct radeon_crtc *test_radeon_crtc; @@ -1749,6 +1750,10 @@ static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) test_radeon_crtc = to_radeon_crtc(test_crtc); if (test_radeon_crtc->encoder && ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { + /* PPLL2 is exclusive to UNIPHYA on DCE61 */ + if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && + test_radeon_crtc->pll_id == ATOM_PPLL2) + continue; /* for DP use the same PLL for all */ if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) return test_radeon_crtc->pll_id; @@ -1770,6 +1775,7 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; struct drm_crtc *test_crtc; struct radeon_crtc *test_radeon_crtc; u32 adjusted_clock, test_adjusted_clock; @@ -1785,6 +1791,10 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) test_radeon_crtc = to_radeon_crtc(test_crtc); if (test_radeon_crtc->encoder && !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { + /* PPLL2 is exclusive to UNIPHYA on DCE61 */ + if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && + test_radeon_crtc->pll_id == ATOM_PPLL2) + continue; /* check if we are already driving this connector with another crtc */ if (test_radeon_crtc->connector == radeon_crtc->connector) { /* if we are, return that pll */ -- 2.5.5