From patchwork Fri Aug 8 13:31:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 4696321 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7174DC0338 for ; Fri, 8 Aug 2014 13:32:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 90B0B2018E for ; Fri, 8 Aug 2014 13:32:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5D01F200E3 for ; Fri, 8 Aug 2014 13:31:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 039516E03B; Fri, 8 Aug 2014 06:31:58 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qg0-f49.google.com (mail-qg0-f49.google.com [209.85.192.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EA7F6E03B for ; Fri, 8 Aug 2014 06:31:56 -0700 (PDT) Received: by mail-qg0-f49.google.com with SMTP id j107so5954159qga.36 for ; Fri, 08 Aug 2014 06:31:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=9Jl05tdQxOXGSYWVo+rl9xpRFgQv79PNLxNT1zpzYzg=; b=Km98LamMWPCMr53ub2mUAtapdfObpbGW+IE5apmh8PPf52ORPh+w2B2C+vuyDizklY xls0RX28Cy8lx/j8TB2ToLhPJNyO/AvHQ8Wonw/rtklmjQ9mdrsUVyQNQ1tkYXoTozg/ U5RkJ95Dc+YX56CJtkPfqYGR/S4fj9Qeg+6t8NsHK0d9MmG/glhYupe9JX/ufpdQXr9j Y1xKh7FsIpIXR/UdI9YfdOUalo5zMyjf8kZzzgjV/iT9Ovrp3TtoXIwZGQuBUmJIkUEM Y7tUus+bs3EMBFbyC7q8C8B6w8NoSrU5XVrVCaI7KGMVdYwkAYaceN0IP3MQjD4EgKMe BZ/Q== MIME-Version: 1.0 X-Received: by 10.224.21.9 with SMTP id h9mr36750166qab.67.1407504714793; Fri, 08 Aug 2014 06:31:54 -0700 (PDT) Received: by 10.140.103.71 with HTTP; Fri, 8 Aug 2014 06:31:54 -0700 (PDT) In-Reply-To: <53E48F55.2090103@daenzer.net> References: <1407397616-23934-1-git-send-email-michel@daenzer.net> <53E4383F.8040806@daenzer.net> <53E48DD2.6040505@vodafone.de> <53E48F55.2090103@daenzer.net> Date: Fri, 8 Aug 2014 09:31:54 -0400 Message-ID: Subject: Re: [PATCH] drm/radeon: Always flush VM again on < CIK From: Alex Deucher To: =?UTF-8?Q?Michel_D=C3=A4nzer?= Cc: Maling list - DRI developers X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Aug 8, 2014 at 4:50 AM, Michel Dänzer wrote: > On 08.08.2014 17:44, Christian König wrote: >>>>> On Thu, Aug 7, 2014 at 3:59 PM, Alex Deucher >>>>> wrote: >>>>>> We should be using PFP as much as possible. Does the attached >>>>>> patch help? >>> Unfortunately not. >> >> Maybe add a readback of the VM base addr pointer to make sure that the >> write has really reached the SBRM? > > I'm not sure what exactly you're thinking of, but I'm happy to test any > patches you guys come up with. :) > Maybe some variant of this patch? Alex diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index dbd9d81..0855da0 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -5007,6 +5007,7 @@ static void si_vm_decode_fault(struct radeon_device *rdev, void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) { struct radeon_ring *ring = &rdev->ring[ridx]; + u32 reg; if (vm == NULL) return; @@ -5017,15 +5018,23 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) WRITE_DATA_DST_SEL(0))); if (vm->id < 8) { - radeon_ring_write(ring, - (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); + reg = (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2; } else { - radeon_ring_write(ring, - (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); + reg = (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2; } + radeon_ring_write(ring, reg); radeon_ring_write(ring, 0); radeon_ring_write(ring, vm->pd_gpu_addr >> 12); + /* wait for the address change to go through */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, 3); /* == */ + radeon_ring_write(ring, reg); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, vm->pd_gpu_addr >> 12); + radeon_ring_write(ring, 0x0fffffff); + radeon_ring_write(ring, 10); + /* flush hdp cache */ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | @@ -5034,6 +5043,14 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) radeon_ring_write(ring, 0); radeon_ring_write(ring, 0x1); + /* clear the response reg */ + radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | + WRITE_DATA_DST_SEL(0))); + radeon_ring_write(ring, VM_INVALIDATE_RESPONSE >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 1 << vm->id); + /* bits 0-15 are the VM contexts0-15 */ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | @@ -5042,6 +5059,15 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) radeon_ring_write(ring, 0); radeon_ring_write(ring, 1 << vm->id); + /* wait for the invalidate */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, 3); /* == */ + radeon_ring_write(ring, VM_INVALIDATE_RESPONSE >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 1 << vm->id); + radeon_ring_write(ring, 1 << vm->id); + radeon_ring_write(ring, 10); + /* sync PFP to ME, otherwise we might get invalid PFP reads */ radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, 0x0);