From patchwork Mon Sep 8 17:36:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 4864151 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E788C9F32F for ; Mon, 8 Sep 2014 17:36:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F29832011D for ; Mon, 8 Sep 2014 17:36:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7DC65200FF for ; Mon, 8 Sep 2014 17:36:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 578AF6E301; Mon, 8 Sep 2014 10:36:30 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qa0-f42.google.com (mail-qa0-f42.google.com [209.85.216.42]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E9356E2FA; Mon, 8 Sep 2014 10:36:28 -0700 (PDT) Received: by mail-qa0-f42.google.com with SMTP id dc16so10439412qab.1 for ; Mon, 08 Sep 2014 10:36:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=lJHdAaTVBIG1mDvZ/6uLWdFzUoEaxvFHMHa5uRSZgxc=; b=yIrnUY1JwY2Qttx4YUbSBGe5lGFgJ4ztv6yr0gnXnRrhLTtVAFdK3Qq9Sn6pduOi2F /GO806zfjjfd9N4Kgl0buvWwfphF6z3NQsvjm5gw5JWaUG83VcXR5j4fOVeeBO6xnaWO +eaOPxQo2gkiq/o0fV9/d24/wci/8nTZZX+VJKHJzYe8qPBMm32GmAytBFHnOjYItNKl 1eXHDbvjgtRsv8G/oRXXPQZ+mARu3gNq3u9+heCQREgSHy9xAf4pMmb6ESIoEjaFQ+jl TNwb5ibcHFHur42LNYsMiZiavxFHRNeeFIQ7i4k0NCYk640kQk6ezza+rXoTBIZU/iCM DH9w== MIME-Version: 1.0 X-Received: by 10.224.156.201 with SMTP id y9mr43508531qaw.53.1410197787143; Mon, 08 Sep 2014 10:36:27 -0700 (PDT) Received: by 10.140.94.75 with HTTP; Mon, 8 Sep 2014 10:36:27 -0700 (PDT) In-Reply-To: <53FFDB6B.5050105@daenzer.net> References: <1409208961-7322-1-git-send-email-michel@daenzer.net> <53FEEEF4.7030401@vodafone.de> <53FFDB6B.5050105@daenzer.net> Date: Mon, 8 Sep 2014 13:36:27 -0400 Message-ID: Subject: Re: [Mesa-dev] [PATCH] drm/radeon: Add RADEON_GEM_CPU_ACCESS BO creation flag From: Alex Deucher To: =?UTF-8?Q?Michel_D=C3=A4nzer?= Cc: "mesa-dev@lists.freedesktop.org" , Maling list - DRI developers X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Aug 28, 2014 at 9:46 PM, Michel Dänzer wrote: > On 29.08.2014 00:01, Alex Deucher wrote: >> On Thu, Aug 28, 2014 at 4:57 AM, Christian König >> wrote: >>> Am 28.08.2014 um 08:56 schrieb Michel Dänzer: >>> >>>> From: Michel Dänzer >>>> >>>> This flag is a hint that userspace expects the BO to be accessed by the >>>> CPU. We can use that hint to prevent such BOs from ever being stored in >>>> the CPU inaccessible part of VRAM. >>>> >>>> Signed-off-by: Michel Dänzer >>> >>> >>> This patch is Reviewed-by: Christian König >> >> Applied to my -next tree. > > Thanks! > > >>> I think we need a similar negative flags as well, e.g. >>> RADEON_GEM_NO_CPU_ACCESS. >>> >>> This way we can stop forcing buffers into the visible VRAM while pinning >>> them for scanout. >> >> How about the attached patch? > > [...] > >> diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c >> index 09b039a..b71e8e0 100644 >> --- a/drivers/gpu/drm/radeon/radeon_object.c >> +++ b/drivers/gpu/drm/radeon/radeon_object.c >> @@ -314,10 +314,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, >> unsigned lpfn = 0; >> >> /* force to pin into visible video ram */ >> - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) >> - lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; >> - else >> + if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) { >> + if (bo->flags & RADEON_GEM_NO_CPU_ACCESS) >> + lpfn = bo->rdev->mc.real_vram_size >> PAGE_SHIFT; >> + else >> + lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; > > lpfn can be left at 0 if RADEON_GEM_NO_CPU_ACCESS is set, so this can > be simplified to: > > if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS)) > lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; > > >> diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h >> index f755f20..d2346fd 100644 >> --- a/include/uapi/drm/radeon_drm.h >> +++ b/include/uapi/drm/radeon_drm.h >> @@ -803,6 +803,8 @@ struct drm_radeon_gem_info { >> #define RADEON_GEM_GTT_WC (1 << 2) >> /* BO is expected to be accessed by the CPU */ >> #define RADEON_GEM_CPU_ACCESS (1 << 3) >> +/* BO is expected to not be accessed by the CPU */ >> +#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) > > I'd use stronger wording for this, e.g. > > /* CPU access is not expected to work for this BO */ Updated version with comments integrated. Alex Reviewed-by: Michel Dänzer From 8e0fe1b090f75e5b7cadc9c316d1a9e3668c8ed2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 28 Aug 2014 10:59:05 -0400 Subject: [PATCH] drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag (v2) Allows pinning of buffers in the non-CPU visible portion of vram. v2: incorporate Michel's comments. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_object.c | 8 +++++--- include/uapi/drm/radeon_drm.h | 2 ++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index eef60aa..c7ad231d 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -314,10 +314,12 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, unsigned lpfn = 0; /* force to pin into visible video ram */ - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) - lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; - else + if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) { + if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS)) + lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + } else { lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */ + } if (max_offset) lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT)); diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index f755f20..50d0fb4 100644 --- a/include/uapi/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h @@ -803,6 +803,8 @@ struct drm_radeon_gem_info { #define RADEON_GEM_GTT_WC (1 << 2) /* BO is expected to be accessed by the CPU */ #define RADEON_GEM_CPU_ACCESS (1 << 3) +/* CPU access is not expected to work for this BO */ +#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) struct drm_radeon_gem_create { uint64_t size; -- 1.8.3.1