[pull] drm/msm: drm-msm-fixes-2025-02-20 for v6.14-rc4

Pull-request

https://gitlab.freedesktop.org/drm/msm.git tags/drm-msm-fixes-2025-02-20

Message

Rob Clark Feb. 20, 2025, 5:33 p.m. UTC

Hi Dave, Simona,

A few fixes for v6.14, as described below.

The following changes since commit 866e43b945bf98f8e807dfa45eca92f931f3a032:

  drm/msm: UAPI error reporting (2025-01-03 07:20:28 -0800)

are available in the Git repository at:

  https://gitlab.freedesktop.org/drm/msm.git tags/drm-msm-fixes-2025-02-20

for you to fetch changes up to 73f69c6be2a9f22c31c775ec03c6c286bfe12cfa:

  drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing
bitclk source (2025-02-15 11:46:42 -0800)

----------------------------------------------------------------
Fixes for v6.14-rc4

Display:
* More catalog fixes:
 - to skip watchdog programming through top block if its not present
 - fix the setting of WB mask to ensure the WB input control is programmed
   correctly through ping-pong
 - drop lm_pair for sm6150 as that chipset does not have any 3dmerge block
* Fix the mode validation logic for DP/eDP to account for widebus (2ppc)
  to allow high clock resolutions
* Fix to disable dither during encoder disable as otherwise this was
  causing kms_writeback failure due to resource sharing between
* WB and DSI paths as DSI uses dither but WB does not
* Fixes for virtual planes, namely to drop extraneous return and fix
  uninitialized variables
* Fix to avoid spill-over of DSC encoder block bits when programming
  the bits-per-component
* Fixes in the DSI PHY to protect against concurrent access of
  PHY_CMN_CLK_CFG regs between clock and display drivers

Core/GPU:
* Fix non-blocking fence wait incorrectly rounding up to 1 jiffy timeout
* Only print GMU fw version once, instead of each time the GPU resumes

----------------------------------------------------------------
Abhinav Kumar (1):
      drm/msm/dp: account for widebus and yuv420 during mode validation

Dmitry Baryshkov (3):
      drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450
      drm/msm/dpu: enable DPU_WB_INPUT_CTRL for DPU 5.x
      drm/msm/dpu: correct LM pairing for SM6150

Ethan Carter Edwards (1):
      drm/msm/dpu: Fix uninitialized variable

Jessica Zhang (2):
      drm/msm/dpu: Disable dither in phys encoder cleanup
      drm/msm/dpu: Drop extraneous return in dpu_crtc_reassign_planes()

Konrad Dybcio (1):
      drm/msm/a6xx: Only print the GMU firmware version once

Krzysztof Kozlowski (3):
      drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side
      drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver
      drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing
bitclk source

Marijn Suijten (1):
      drm/msm/dpu: Don't leak bits_per_component into random DSC_ENC fields

Rob Clark (1):
      drm/msm: Avoid rounding up to one jiffy

 drivers/gpu/drm/msm/adreno/a6xx_gmu.c              |  8 ++--
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h |  2 +-
 .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h    |  2 +-
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h |  2 -
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |  2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  3 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c         |  3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c         |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          |  7 ++-
 drivers/gpu/drm/msm/dp/dp_display.c                | 11 +++--
 drivers/gpu/drm/msm/dp/dp_drm.c                    |  5 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          | 53 +++++++++++++++-------
 drivers/gpu/drm/msm/msm_drv.h                      | 11 ++---
 .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml  | 11 ++++-
 15 files changed, 75 insertions(+), 49 deletions(-)