diff mbox

[RFC,5/8] drm/i2c: nxp-tda998x: fix npix/nline programming

Message ID E1UllM6-00058d-LK@rmk-PC.arm.linux.org.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Russell King June 9, 2013, 7:32 p.m. UTC
The npix/nline registers are supposed to be programmed with the total
number of pixels/lines, not the displayed pixels/lines, and not minus
one either.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 drivers/gpu/drm/i2c/tda998x_drv.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

Comments

Sebastian Hesselbarth June 9, 2013, 8:02 p.m. UTC | #1
On 06/09/2013 09:32 PM, Russell King wrote:
> The npix/nline registers are supposed to be programmed with the total
> number of pixels/lines, not the displayed pixels/lines, and not minus
> one either.
>
> Signed-off-by: Russell King<rmk+kernel@arm.linux.org.uk>
> ---

Russell, Rob,

I have patches fixing TDA998x sync generation for progressive video.
They are based on TDA9983b datasheet [1]. TDA998x expects ITU-style
sync with positive hblank/vblank (or VESA-style hsync/vsync plus
refpix/refline). The patches make TDA998x behave as transparent as
possible, i.e. invert input sync signals as required and revert for
output sync as requested by EDID. I have measured a bunch of modes
with an oszilloscope near-end (TDA998x input) and far-end (DVI receiver
output) and they are pixel- and line-true.

Unfortunately, I have no receiver allowing me to also fix interlaced
sync generation but with progressive working, that shouldn't be that
hard to implement.

Will clean-up patches next week and rebase on Russell's RFC.

Sebastian

[1]
http://pdf1.alldatasheet.com/datasheet-pdf/view/347888/NXP/TDA9983B.html
diff mbox

Patch

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index dc0428d..cd1526c 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -587,8 +587,8 @@  tda998x_encoder_mode_set(struct drm_encoder *encoder,
 		reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL);
 
 	reg_write(encoder, REG_VIDFORMAT, 0x00);
-	reg_write16(encoder, REG_NPIX_MSB, mode->hdisplay - 1);
-	reg_write16(encoder, REG_NLINE_MSB, mode->vdisplay - 1);
+	reg_write16(encoder, REG_NPIX_MSB, mode->htotal);
+	reg_write16(encoder, REG_NLINE_MSB, mode->vtotal);
 	reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start);
 	reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end);
 	reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start);