diff mbox series

drm/amdgpu: Fix typo "acccess" and improve the comment style here

Message ID F25A139789E87C3E+20240920022755.1162495-1-wangyuli@uniontech.com (mailing list archive)
State New, archived
Headers show
Series drm/amdgpu: Fix typo "acccess" and improve the comment style here | expand

Commit Message

WangYuli Sept. 20, 2024, 2:27 a.m. UTC
There are some spelling mistakes of 'acccess' in comments which
should be instead of 'access'.

And the comment style should be like this:
 /*
  * Text
  * Text
  */

Suggested-by: Christian König <christian.koenig@amd.com>
Link: https://lore.kernel.org/all/f75fbe30-528e-404f-97e4-854d27d7a401@amd.com/
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://lore.kernel.org/all/0c768bf6-bc19-43de-a30b-ff5e3ddfd0b3@suse.de/
Signed-off-by: WangYuli <wangyuli@uniontech.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c  | 6 ++++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

Comments

Christian König Sept. 20, 2024, 6:28 a.m. UTC | #1
Am 20.09.24 um 04:27 schrieb WangYuli:
> There are some spelling mistakes of 'acccess' in comments which
> should be instead of 'access'.
>
> And the comment style should be like this:
>   /*
>    * Text
>    * Text
>    */
>
> Suggested-by: Christian König <christian.koenig@amd.com>
> Link: https://lore.kernel.org/all/f75fbe30-528e-404f-97e4-854d27d7a401@amd.com/
> Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
> Link: https://lore.kernel.org/all/0c768bf6-bc19-43de-a30b-ff5e3ddfd0b3@suse.de/
> Signed-off-by: WangYuli <wangyuli@uniontech.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c  | 6 ++++--
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++--
>   2 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index d3e8be82a172..33fd2da49a2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -1893,8 +1893,10 @@ static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
>   	soc21_grbm_select(adev, 0, 0, 0, 0);
>   	mutex_unlock(&adev->srbm_mutex);
>   
> -	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
> -	   acccess. These should be enabled by FW for target VMIDs. */
> +	/*
> +	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
> +	 * access. These should be enabled by FW for target VMIDs.
> +	 */
>   	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
>   		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
>   		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 408e5600bb61..57b55b6d797d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -1247,8 +1247,10 @@ static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
>   	soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
>   	mutex_unlock(&adev->srbm_mutex);
>   
> -	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
> -	   acccess. These should be enabled by FW for target VMIDs. */
> +	/*
> +	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
> +	 * access. These should be enabled by FW for target VMIDs.
> +	 */
>   	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
>   		WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
>   		WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
Alex Deucher Sept. 24, 2024, 4:08 p.m. UTC | #2
Applied.  Thanks!

Alex

On Fri, Sep 20, 2024 at 2:29 AM Christian König
<christian.koenig@amd.com> wrote:
>
> Am 20.09.24 um 04:27 schrieb WangYuli:
> > There are some spelling mistakes of 'acccess' in comments which
> > should be instead of 'access'.
> >
> > And the comment style should be like this:
> >   /*
> >    * Text
> >    * Text
> >    */
> >
> > Suggested-by: Christian König <christian.koenig@amd.com>
> > Link: https://lore.kernel.org/all/f75fbe30-528e-404f-97e4-854d27d7a401@amd.com/
> > Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
> > Link: https://lore.kernel.org/all/0c768bf6-bc19-43de-a30b-ff5e3ddfd0b3@suse.de/
> > Signed-off-by: WangYuli <wangyuli@uniontech.com>
>
> Reviewed-by: Christian König <christian.koenig@amd.com>
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c  | 6 ++++--
> >   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++--
> >   2 files changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > index d3e8be82a172..33fd2da49a2a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > @@ -1893,8 +1893,10 @@ static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
> >       soc21_grbm_select(adev, 0, 0, 0, 0);
> >       mutex_unlock(&adev->srbm_mutex);
> >
> > -     /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> > -        acccess. These should be enabled by FW for target VMIDs. */
> > +     /*
> > +      * Initialize all compute VMIDs to have no GDS, GWS, or OA
> > +      * access. These should be enabled by FW for target VMIDs.
> > +      */
> >       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> >               WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
> >               WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> > index 408e5600bb61..57b55b6d797d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> > @@ -1247,8 +1247,10 @@ static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
> >       soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
> >       mutex_unlock(&adev->srbm_mutex);
> >
> > -     /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> > -        acccess. These should be enabled by FW for target VMIDs. */
> > +     /*
> > +      * Initialize all compute VMIDs to have no GDS, GWS, or OA
> > +      * access. These should be enabled by FW for target VMIDs.
> > +      */
> >       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> >               WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
> >               WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index d3e8be82a172..33fd2da49a2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1893,8 +1893,10 @@  static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
 	soc21_grbm_select(adev, 0, 0, 0, 0);
 	mutex_unlock(&adev->srbm_mutex);
 
-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
-	   acccess. These should be enabled by FW for target VMIDs. */
+	/*
+	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
+	 * access. These should be enabled by FW for target VMIDs.
+	 */
 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 408e5600bb61..57b55b6d797d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1247,8 +1247,10 @@  static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
 	soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
 	mutex_unlock(&adev->srbm_mutex);
 
-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
-	   acccess. These should be enabled by FW for target VMIDs. */
+	/*
+	 * Initialize all compute VMIDs to have no GDS, GWS, or OA
+	 * access. These should be enabled by FW for target VMIDs.
+	 */
 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 		WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
 		WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);