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Mon, 6 Jan 2020 20:47:43 +0000 Received: from bionic.localdomain (98.128.173.80) by AM6P195CA0080.EURP195.PROD.OUTLOOK.COM (2603:10a6:209:86::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2602.10 via Frontend Transport; Mon, 6 Jan 2020 20:47:42 +0000 From: Jonas Karlman To: Heiko Stuebner , Sandy Huang Subject: [PATCH 04/15] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write Thread-Topic: [PATCH 04/15] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg write Thread-Index: AQHVxNKKLxyL4Q0vOE22PNhI5tid5A== Date: Mon, 6 Jan 2020 20:47:43 +0000 Message-ID: References: <20200106204723.5889-1-jonas@kwiboo.se> In-Reply-To: <20200106204723.5889-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6P195CA0080.EURP195.PROD.OUTLOOK.COM (2603:10a6:209:86::21) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:8C19569506F8BD7642EB2068ACC681F4CCFF9E0FBB922D8AF839168E0728C830; UpperCasedChecksum:208474F13C68AC48892D2A1F3171ED9F280F3CF3166E792915F58D934847E662; SizeAsReceived:8214; Count:51 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-tmn: [d4h1GFYe1CbrN0nWU9c/hx+yzaPUmp2D] x-microsoft-original-message-id: <20200106204723.5889-4-jonas@kwiboo.se> x-ms-publictraffictype: Email x-incomingheadercount: 51 x-eopattributedmessage: 0 x-ms-office365-filtering-correlation-id: 33835552-4958-454e-2c9e-08d792e9ad47 x-ms-traffictypediagnostic: VE1EUR02HT081: x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: phhp6ZKkFuy6X8DwBCXpXOmTFFnDtvCQkrT5GM/NcCrNjmcrQU5DblzdC/1rekEzuXPVmxUQbw7hraKXS4zwUytGPbINhoN10OFh1Z/q6M1ZXAnS5UOyg+vrVRS2HXArk8URa1tM2zw3PnP8eK1kzriyC+1zoPBOMta/ebqxRXC2DGes22hS+Ty2c6qnkpch x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 33835552-4958-454e-2c9e-08d792e9ad47 X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jan 2020 20:47:43.1490 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1EUR02HT081 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Jonas Karlman , David Airlie , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , Kishon Vijay Abraham I , "linux-rockchip@lists.infradead.org" , Rob Herring , "linux-arm-kernel@lists.infradead.org" , Zheng Yang Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 06db69c8373e..3a59a6da0440 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); if (cfg->postdiv == 1) { - inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | RK3328_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | + RK3328_POST_PLL_POWER_DOWN); } else { v = (cfg->postdiv / 2) - 1; v &= RK3328_POST_PLL_POST_DIV_MASK; @@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | RK3328_POST_PLL_PRE_DIV(cfg->prediv)); inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | - RK3328_POST_PLL_REFCLK_SEL_TMDS); + RK3328_POST_PLL_REFCLK_SEL_TMDS | + RK3328_POST_PLL_POWER_DOWN); } for (v = 0; v < 14; v++)