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Mon, 6 Jan 2020 20:48:28 +0000 Received: from bionic.localdomain (98.128.173.80) by BEXP281CA0004.DEUP281.PROD.OUTLOOK.COM (2603:10a6:b10::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2602.12 via Frontend Transport; Mon, 6 Jan 2020 20:48:27 +0000 From: Jonas Karlman To: Heiko Stuebner , Sandy Huang Subject: [PATCH 08/15] drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328 Thread-Topic: [PATCH 08/15] drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328 Thread-Index: AQHVxNKmR0W4jadvKEivva24BcWyzA== Date: Mon, 6 Jan 2020 20:48:28 +0000 Message-ID: References: <20200106204812.5944-1-jonas@kwiboo.se> In-Reply-To: <20200106204812.5944-1-jonas@kwiboo.se> Accept-Language: sv-SE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BEXP281CA0004.DEUP281.PROD.OUTLOOK.COM (2603:10a6:b10::14) To HE1PR06MB4011.eurprd06.prod.outlook.com (2603:10a6:7:9c::32) x-incomingtopheadermarker: OriginalChecksum:A19395B89A6FDC5BAC83C828B43BC340A6BED94B82C857ED840F0AA645130AAF; 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Lets validate the mode clock rate against the pre pll config and filter out any mode with a clock rate returning error from clk_round_rate(). Signed-off-by: Jonas Karlman --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index fae38b323a0c..45fcdce3f27f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -245,6 +245,22 @@ static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) { } +static enum drm_mode_status +dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + long rate; + + if (hdmi->vpll_clk) { + rate = clk_round_rate(hdmi->vpll_clk, mode->clock * 1000); + if (rate < 0) + return MODE_CLOCK_RANGE; + } + + return MODE_OK; +} + static bool dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, @@ -306,6 +322,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { + .mode_valid = dw_hdmi_rockchip_encoder_mode_valid, .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, .mode_set = dw_hdmi_rockchip_encoder_mode_set, .enable = dw_hdmi_rockchip_encoder_enable,