| Message ID | HE1PR06MB40118544456FC5461F49DDE8AC2E0@HE1PR06MB4011.eurprd06.prod.outlook.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [for,5.5] phy/rockchip: inno-hdmi: round clock rate down to closest 1000 Hz | expand |
Hi, On Mon, Dec 23, 2019 at 12:49 AM Jonas Karlman <jonas@kwiboo.se> wrote: > > Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") > changed what rate clk_round_rate() is called with, an additional 999 Hz > added to the requsted mode clock. This has caused a regression on RK3328 > and presumably also on RK3228 because the inno-hdmi-phy clock requires an > exact match of the requested rate in the pre pll config table. > > When an exact match is not found the parent clock rate (24MHz) is returned > to the clk_round_rate() caller. This cause wrong pixel clock to be used and > result in no-signal when configuring a mode on RK3328. > > Fix this by rounding the rate down to closest 1000 Hz in round_rate func, > this allows an exact match to be found in pre pll config table. > > Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- > drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++++ > 1 file changed, 4 insertions(+) Sorry for the regression and thanks for the fix. It seems sane to me since you're just matching against your own table and all the rates there are all in kHz. Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 2b97fb1185a0..9ca20c947283 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -603,6 +603,8 @@ static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, { const struct pre_pll_config *cfg = pre_pll_cfg_table; + rate = (rate / 1000) * 1000; + for (; cfg->pixclock != 0; cfg++) if (cfg->pixclock == rate && !cfg->fracdiv) break; @@ -755,6 +757,8 @@ static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, { const struct pre_pll_config *cfg = pre_pll_cfg_table; + rate = (rate / 1000) * 1000; + for (; cfg->pixclock != 0; cfg++) if (cfg->pixclock == rate) break;
Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") changed what rate clk_round_rate() is called with, an additional 999 Hz added to the requsted mode clock. This has caused a regression on RK3328 and presumably also on RK3228 because the inno-hdmi-phy clock requires an exact match of the requested rate in the pre pll config table. When an exact match is not found the parent clock rate (24MHz) is returned to the clk_round_rate() caller. This cause wrong pixel clock to be used and result in no-signal when configuring a mode on RK3328. Fix this by rounding the rate down to closest 1000 Hz in round_rate func, this allows an exact match to be found in pre pll config table. Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++++ 1 file changed, 4 insertions(+)