From patchwork Thu Jul 14 12:06:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12917791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FBADC43334 for ; Thu, 14 Jul 2022 12:07:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CF93112921; Thu, 14 Jul 2022 12:06:38 +0000 (UTC) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A3AA112921; Thu, 14 Jul 2022 12:06:33 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CBB3A61E96; Thu, 14 Jul 2022 12:06:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B0B07C341DF; Thu, 14 Jul 2022 12:06:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657800390; bh=HQ757VXRDIBLfr8i1wjw+P/iX240DqJQqnlcI4nhgKY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YpshvzwA5HQ+kz50KlsBr04Sfu518nEUJNjziXiAOag4PJ9E91bzU2Tk7Gth3p6q8 Hh07dHXttmYBjbjF/BDjZOVO2Ji3tAx+XoNC6kSDjHjzlwIehfnEedgjhvXcnJs3bF TlyqpRaqv+d0kGvAoNuwl7QFHJayJ+2bKpME/s0DeTQIRF1vD9RuRgZHrg87FGWQEU w0iCGwVqrvxwhl/dO032FlLoDdWhUVseuTT7eEVulzv5vXHQDvZE+I1DsqrLDVSCpu apBUT0Hq2f2P95NETGLAytLfdKnQqHU/bixOjg7sbR/u0b4dKZoKW+f9d7M00d6aSw MPlXVxu6CNX8Q== Received: from mchehab by mail.kernel.org with local (Exim 4.95) (envelope-from ) id 1oBxbw-0059tU-7T; Thu, 14 Jul 2022 13:06:28 +0100 From: Mauro Carvalho Chehab To: Subject: [PATCH v2 20/21] drm/i915/guc: describe enum intel_guc_tlb_invalidation_type Date: Thu, 14 Jul 2022 13:06:25 +0100 Message-Id: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , Tvrtko Ursulin , Borislav Petkov , Alan Previn , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Prathap Kumar Valsan , Rodrigo Vivi , Vinay Belgaumkar , Mauro Carvalho Chehab , intel-gfx@lists.freedesktop.org, John Harrison , Michal Wajdeczko Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a description for intel_guc_tlb_invalidation_type enum. Signed-off-by: Mauro Carvalho Chehab --- To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@kernel.org/ drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index 5c019856a269..e97065c62d28 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -187,6 +187,18 @@ enum intel_guc_state_capture_event_status { /* Flush PPC or SMRO caches along with TLB invalidation request */ #define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31) +/** + * enum intel_guc_tlb_invalidation_type - type of TLB cache invalidation + * + * @INTEL_GUC_TLB_INVAL_FULL: + * Global TLB invalidation + * @INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE: + * Page-selective TLB cache invalidation + * @INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX: + * Context-selective TLB cache invalidation + * @INTEL_GUC_TLB_INVAL_GUC: + * Invalidate TLB on GuC itself + */ enum intel_guc_tlb_invalidation_type { INTEL_GUC_TLB_INVAL_FULL = 0x0, INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,