| Message ID | a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: dp 2.0 enabling prep work | expand |
On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: > There's a new register pair for 128b/132b mode where you need to set the > pixel clock in Hz. > > v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper > > Bspec: 54128 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d104441344c0..97af19fd9780 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > clear_act_sent(encoder, pipe_config); > > + if (intel_dp_is_uhbr(pipe_config)) { > + const struct drm_display_mode *adjusted_mode = > + &pipe_config->hw.adjusted_mode; > + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); > + > + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); > + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); > + } > + > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, > -- > 2.30.2
On Fri, 17 Sep 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: >> There's a new register pair for 128b/132b mode where you need to set the >> pixel clock in Hz. >> >> v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper >> >> Bspec: 54128 >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks for the reviews, pushed up to and including this one. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> index d104441344c0..97af19fd9780 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, >> >> clear_act_sent(encoder, pipe_config); >> >> + if (intel_dp_is_uhbr(pipe_config)) { >> + const struct drm_display_mode *adjusted_mode = >> + &pipe_config->hw.adjusted_mode; >> + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); >> + >> + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); >> + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); >> + } >> + >> intel_ddi_enable_transcoder_func(encoder, pipe_config); >> >> intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, >> -- >> 2.30.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..97af19fd9780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, clear_act_sent(encoder, pipe_config); + if (intel_dp_is_uhbr(pipe_config)) { + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); + + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); + } + intel_ddi_enable_transcoder_func(encoder, pipe_config); intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz. v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper Bspec: 54128 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ 1 file changed, 11 insertions(+)