@@ -338,7 +338,7 @@ static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
* @ch_regs: memory mapped register base
* @clk: dma controller clock
* @save_imr: interrupt mask register that is saved on suspend/resume cycle
- * @all_chan_mask: all channels availlable in a mask
+ * @all_chan_mask: all channels available in a mask
* @dma_desc_pool: base of DMA descriptor region (DMA address)
* @chan: channels table to store at_dma_chan structures
*/
@@ -462,7 +462,7 @@ static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
/**
* set_desc_eol - set end-of-link to descriptor so it will end transfer
- * @desc: descriptor, signle or at the end of a chain, to end chain on
+ * @desc: descriptor, single or at the end of a chain, to end chain on
*/
static void set_desc_eol(struct at_desc *desc)
{
s/availlable/available/ s/signle/single/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> --- drivers/dma/at_hdmac_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.26.3