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Fri, 8 Apr 2022 10:33:18 +0000 From: Sandor Yu To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, andrzej.hajda@intel.com, narmstrong@baylibre.com, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, hverkuil-cisco@xs4all.nl Subject: [PATCH v2 4/5] drm: bridge: dw_hdmi: add reset function for PHY GEN1 Date: Fri, 8 Apr 2022 18:32:27 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: X-ClientProxiedBy: SGXP274CA0017.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::29) To DB7PR04MB5450.eurprd04.prod.outlook.com (2603:10a6:10:86::11) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b92eda1d-1342-4852-2e33-08da194b3273 X-MS-TrafficTypeDiagnostic: VI1PR0402MB3405:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VRiJ46s7G9tMMRzJBFLuahvorIiK/9ywLP8U5qwbmb1yk8F9hkNIIFSXtYMkFMUGAO4GXZsPkMCUtagS1OGexzsK/rTbv53t6NjNxN79Z8e2oZprVSKv2o30PGS7ouPNGmsz1pN/K63i1Os7EVMszJTiWam/Fqbh8QPlNrySD0NH9Us+l7Ky7WOkErdtU1lYaA7gKecVos/iMljHFuagh0jRsdgwZ8mN/4yUzYB9I5YVkA1J1cVXV8PgV5zyDEV8kxu4HzymfVAlnjy07n3bDBIu6qnm+YC73e6n8fkMZlaV0Bdy4pYr7MQV/Gim3+laja93/qhdXrbiSnHB6EJevPy8S1qhJj9L8M70URcV1EoOkM1FteQJ+cpoy6JZcvxDU1V8lHto5O1SlsulXkN+4W/ZwG6hsjbBXA4zSPWaWj8bZAGSUYRsBmnG5IEEo4VCzzCs3/EtTcOUOkmT/JkQ5LlE7Yy2nuOCZVIiPL995rs7dsv/5JCB5C9g0FrvkWvDI6E3LH2F1h9lGmOmYZb2+LZXZCyF5H4phwI5KdNAuv5uoT8VundRz8rW4vu7H6Ee5pwFxhcuaDmJTejtGKSDaoQQBubJT9HfGNxsU6CWC4o+GqIKDnQk2r10BLLTESIHaWxdpiKkyHE+vKHDPqxLrXycpEKxKGIHcWQqSUtHz3rWlYcTqinRrRk5f8PP2lHznsqmFgejeCa+shTntcWsSw== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset. Add dw_hdmi_phy_gen1_reset function for PHY GEN1. Signed-off-by: Sandor Yu Reviewed-by: Neil Armstrong Acked-by: Jernej Skrabec --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++--- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +- include/drm/bridge/dw_hdmi.h | 4 +++- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 5a7ec066e37a..13270d96e5be 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1369,13 +1369,21 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) HDMI_PHY_CONF0_SELDIPIF_MASK); } -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) +{ + /* PHY reset. The reset signal is active low on Gen1 PHYs. */ + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); +} +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); + +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) { /* PHY reset. The reset signal is active high on Gen2 PHYs. */ hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); } -EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) { @@ -1529,7 +1537,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, if (phy->has_svsret) dw_hdmi_phy_enable_svsret(hdmi, 1); - dw_hdmi_phy_reset(hdmi); + dw_hdmi_phy_gen2_reset(hdmi); hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 5e2b0175df36..2860e6bff8b7 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi, dw_hdmi_phy_gen2_txpwron(hdmi, 0); dw_hdmi_phy_gen2_pddq(hdmi, 1); - dw_hdmi_phy_reset(hdmi); + dw_hdmi_phy_gen2_reset(hdmi); dw_hdmi_phy_gen2_pddq(hdmi, 0); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index 2a1f85f9a8a3..70082f80a8c8 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, unsigned char addr); +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi); + void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi); enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data);