From patchwork Wed May 29 08:00:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 13678108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 983F0C25B75 for ; Wed, 29 May 2024 08:02:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E69E11343D; Wed, 29 May 2024 08:02:36 +0000 (UTC) Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by gabe.freedesktop.org (Postfix) with ESMTP id D87E0112E8A for ; Wed, 29 May 2024 08:01:53 +0000 (UTC) Received: from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 5AC691C03A3; Wed, 29 May 2024 17:01:51 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Thomas Gleixner , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Neil Armstrong , Chris Morgan , Sebastian Reichel , Linus Walleij , Arnd Bergmann , Masahiro Yamada , Baoquan He , Andrew Morton , Guenter Roeck , Kefeng Wang , Stephen Rothwell , Azeem Shaikh , Guo Ren , Max Filippov , Jernej Skrabec , Herve Codina , Andy Shevchenko , Anup Patel , Jacky Huang , Hugo Villeneuve , Jonathan Corbet , Wolfram Sang , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig?= , Christophe JAILLET , Sam Ravnborg , Javier Martinez Canillas , Sergey Shtylyov , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [DO NOT MERGE v8 13/36] dt-bindings: clock: sh7750-cpg: Add renesas, sh7750-cpg header. Date: Wed, 29 May 2024 17:00:59 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SH7750 CPG Clock output define. Signed-off-by: Yoshinori Sato --- .../bindings/clock/renesas,sh7750-cpg.yaml | 107 ++++++++++++++++++ include/dt-bindings/clock/sh7750-cpg.h | 26 +++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 include/dt-bindings/clock/sh7750-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file mode 100644 index 000000000000..0cdcab6fb4bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + enum: + - renesas,sh7750-cpg # SH7750 + - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + + reg: + minItems: 1 + maxItems: 2 + + reg-names: true + + clocks: + maxItems: 1 + + clock-names: + const: extal + + '#clock-cells': + const: 1 + + renesas,mode: + description: Board-specific settings of the MD[0-2] pins on SoC + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750-cpg + - renesas,sh7750s-cpg + then: + properties: + reg: + maxItems: 1 + reg-names: + items: + - const: FRQCR + + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750r-cpg + - renesas,sh7751-cpg + - renesas,sh7751r-cpg + then: + properties: + reg: + minItems: 2 + reg-names: + items: + - const: FRQCR + - const: CLKSTP00 + +additionalProperties: false + +examples: + - | + #include + cpg: clock-controller@ffc00000 { + compatible = "renesas,sh7751r-cpg"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + clocks = <&extal>; + clock-names = "extal"; + renesas,mode = <0>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/include/dt-bindings/clock/sh7750-cpg.h b/include/dt-bindings/clock/sh7750-cpg.h new file mode 100644 index 000000000000..ec267be91adf --- /dev/null +++ b/include/dt-bindings/clock/sh7750-cpg.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright 2023 Yoshinori Sato + */ + +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ +#define __DT_BINDINGS_CLOCK_SH7750_H__ + +#define SH7750_CPG_PLLOUT 0 + +#define SH7750_CPG_PCK 1 +#define SH7750_CPG_BCK 2 +#define SH7750_CPG_ICK 3 + +#define SH7750_MSTP_SCI 4 +#define SH7750_MSTP_RTC 5 +#define SH7750_MSTP_TMU012 6 +#define SH7750_MSTP_SCIF 7 +#define SH7750_MSTP_DMAC 8 +#define SH7750_MSTP_UBC 9 +#define SH7750_MSTP_SQ 10 +#define SH7750_CSTP_INTC 11 +#define SH7750_CSTP_TMU34 12 +#define SH7750_CSTP_PCIC 13 + +#endif