From patchwork Thu Dec 19 08:23:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 11302791 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 091BC14F6 for ; Thu, 19 Dec 2019 08:23:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA46921D7D for ; Thu, 19 Dec 2019 08:23:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oCM5OJVC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DA46921D7D Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00B206E321; Thu, 19 Dec 2019 08:23:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 792546EAD1 for ; Thu, 19 Dec 2019 08:23:51 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBJ8NTTq122321; Thu, 19 Dec 2019 02:23:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1576743809; bh=LSt5PHn/W84Au3xM6G0khj4qkObbM4ipblw3wB39Gmk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oCM5OJVCYjDMuSH6l3Bo5sZriH6A8hHwvcG/RXLZFVHIREyKPVD4KiJC3NfLxR64s pIwBMD26Mto1pbvTeSWchp1pJNekTbIYjOV5/rYGZPjJTuvLyAfZUxVHvPb6o4j7Aj f0SYQtd6gflUrbwwhs18a1q1nqU6gn6XrZkXlz90= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBJ8NTxa086541 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Dec 2019 02:23:29 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 19 Dec 2019 02:23:28 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 19 Dec 2019 02:23:28 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBJ8NJI6095098; Thu, 19 Dec 2019 02:23:25 -0600 From: Jyri Sarha To: , Subject: [PATCH v4 2/5] dt-bindings: display: ti, am65x-dss: Add dt-schema yaml binding Date: Thu, 19 Dec 2019 10:23:16 +0200 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yamonkar@cadence.com, praneeth@ti.com, sjakhade@cadence.com, robh+dt@kernel.org, peter.ujfalusi@ti.com, tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, subhajit_paul@ti.com, sam@ravnborg.org, maxime@cerno.tech Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add dt-schema yaml bindig for AM65x DSS, AM65x version TI Keystone Display SubSystem. Version history: v2: no change v3: - Add ports node - use allOf in ti,am65x-oldi-io-ctrl to add both $ref and maxItems - Add includes to dts example - reindent dts example v4: - Add descriptions to reg and clocks properties - Remove minItems when its value is the same as maxItems value Signed-off-by: Jyri Sarha --- .../bindings/display/ti/ti,am65x-dss.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml new file mode 100644 index 000000000000..16137770b995 --- /dev/null +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments AM65x Display Subsystem + +maintainers: + - Jyri Sarha + - Tomi Valkeinen + +description: | + The AM65x TI Keystone Display SubSystem with two output ports and + two video planes. The first video port supports OLDI and the second + supports DPI format. The fist plane is full video plane with all + features and the second is a "lite plane" without scaling support. + +properties: + compatible: + const: ti,am65x-dss + + reg: + maxItems: 7 + description: | + Addresses to each DSS memory region described in the SoC's TRM. + The reg-names refer to memory regions as follows: + reg-names: Region Name in TRM: Description: + common DSS0_COMMON DSS common register area + vidl1 DSS0_VIDL1 VIDL1 light video plane + vid DSS0_VID VID video plane + ovr1 DSS0_OVR1 OVR1 overlay manager for vp1 + ovr2 DSS0_OVR2 OVR2 overlay manager for vp2 + vp1 DSS0_VP1 VP1 video port 1 + vp2 DSS0_VP2 VP1 video port 2 + + reg-names: + items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + + clocks: + maxItems: 3 + description: + phandles to clock nodes for DSS functional clock (fck) and video + port 1 and 2 pixel clocks (vp1, vp2). + + clock-names: + items: + - const: fck + - const: vp1 + - const: vp2 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + ports: + type: object + description: + Ports as described in Documentation/devictree/bindings/graph.txt + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: + The DSS OLDI output port node form video port 1 + + port@1: + type: object + description: + The DSS DPI output port node from video port 2 + + required: + - "#address-cells" + - "#size-cells" + + ti,am65x-oldi-io-ctrl: + allOf: + - $ref: "/schemas/types.yaml#/definitions/phandle-array" + - maxItems: 1 + description: + phandle to syscon device node mapping OLDI IO_CTRL registers. + The mapped range should point to OLDI_DAT0_IO_CTRL, map it and + following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL, + and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI + interface to work. + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input memory (from main memory to dispc) bandwidth limit in + bytes per second + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + + dss: dss@04a00000 { + compatible = "ti,am65x-dss"; + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ + <0x0 0x04a06000 0x0 0x1000>, /* vid */ + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + }; + };