| Message ID | fd879fd0595e9e7e47c3442da10a5aede21bf895.1725269643.git.tjakobi@math.uni-bielefeld.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/amd: fix VRR race condition during IRQ handling | expand |
On 2024-09-02 05:40, tjakobi@math.uni-bielefeld.de wrote: > From: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> > > dc_state_destruct() nulls the resource context of the DC state. The pipe > context passed to dcn35_set_drr() is a member of this resource context. > > If dc_state_destruct() is called parallel to the IRQ processing (which > calls dcn35_set_drr() at some point), we can end up using already nulled > function callback fields of struct stream_resource. > > The logic in dcn35_set_drr() already tries to avoid this, by checking tg > against NULL. But if the nulling happens exactly after the NULL check and > before the next access, then we get a race. > > Avoid this by copying tg first to a local variable, and then use this > variable for all the operations. This should work, as long as nobody > frees the resource pool where the timing generators live. > > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3142 > Fixes: 06ad7e164256 ("drm/amd/display: Destroy DC context while keeping DML and DML2") > Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Harry > --- > .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 20 +++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c > index dcced89c07b3..4e77728dac10 100644 > --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c > +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c > @@ -1370,7 +1370,13 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, > params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num; > > for (i = 0; i < num_pipes; i++) { > - if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) { > + /* dc_state_destruct() might null the stream resources, so fetch tg > + * here first to avoid a race condition. The lifetime of the pointee > + * itself (the timing_generator object) is not a problem here. > + */ > + struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; > + > + if ((tg != NULL) && tg->funcs) { > struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing; > struct dc *dc = pipe_ctx[i]->stream->ctx->dc; > > @@ -1383,14 +1389,12 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, > num_frames = 2 * (frame_rate % 60); > } > } > - if (pipe_ctx[i]->stream_res.tg->funcs->set_drr) > - pipe_ctx[i]->stream_res.tg->funcs->set_drr( > - pipe_ctx[i]->stream_res.tg, ¶ms); > + if (tg->funcs->set_drr) > + tg->funcs->set_drr(tg, ¶ms); > if (adjust.v_total_max != 0 && adjust.v_total_min != 0) > - if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control) > - pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( > - pipe_ctx[i]->stream_res.tg, > - event_triggers, num_frames); > + if (tg->funcs->set_static_screen_control) > + tg->funcs->set_static_screen_control( > + tg, event_triggers, num_frames); > } > } > }
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index dcced89c07b3..4e77728dac10 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1370,7 +1370,13 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num; for (i = 0; i < num_pipes; i++) { - if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) { + /* dc_state_destruct() might null the stream resources, so fetch tg + * here first to avoid a race condition. The lifetime of the pointee + * itself (the timing_generator object) is not a problem here. + */ + struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; + + if ((tg != NULL) && tg->funcs) { struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing; struct dc *dc = pipe_ctx[i]->stream->ctx->dc; @@ -1383,14 +1389,12 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, num_frames = 2 * (frame_rate % 60); } } - if (pipe_ctx[i]->stream_res.tg->funcs->set_drr) - pipe_ctx[i]->stream_res.tg->funcs->set_drr( - pipe_ctx[i]->stream_res.tg, ¶ms); + if (tg->funcs->set_drr) + tg->funcs->set_drr(tg, ¶ms); if (adjust.v_total_max != 0 && adjust.v_total_min != 0) - if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control) - pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( - pipe_ctx[i]->stream_res.tg, - event_triggers, num_frames); + if (tg->funcs->set_static_screen_control) + tg->funcs->set_static_screen_control( + tg, event_triggers, num_frames); } } }