From patchwork Mon May 13 01:22:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13662959 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D619A95E for ; Mon, 13 May 2024 01:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715564489; cv=none; b=bdIETRxPsmc8y7SVfPKt2fTFws9Hhq51dI41KUP7Mh3FrTIAYkR/Yywo4kB206lfYFpz3MgzUaXaRqpT8XHavn9HeYpgaC9GV1TMCzEJn6FG/1nwQzWJmfP1SrcSis6s/4P0RafzlMG6tmZoFHvaOjGLYRkn1pFZIXwvCc4eqJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715564489; c=relaxed/simple; bh=HExHPsON4CqrO3LxsKWufOI3fJDGO7ZL+VCYtmf411Q=; h=From:To:Cc:Subject:Date:Message-Id; b=bQCsxJjMwwTXGgx/guFpu/swKADnskOJCVM2eLZh/Q3RG0E2nMR87T/xAtLBjIzapAyDovublXNV1SxGyq24n4tJo8SBYUmtPKjPHIo7uHV8dHOK0pl5TXnypANV/YKR5PvVeqY5H6ZhS0OvJhEQnAbaVo0ETiNJYX3TUfFuOUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5BBBC1A03B8; Mon, 13 May 2024 03:41:20 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E4B971A12E1; Mon, 13 May 2024 03:41:19 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 25A11180226C; Mon, 13 May 2024 09:41:18 +0800 (+08) From: Richard Zhu To: conor@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v5 0/2] Add i.MX8Q HSIO PHY support Date: Mon, 13 May 2024 09:22:02 +0800 Message-Id: <1715563324-6391-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: v5 changes: dt-binding - Fix dt_binding_check errors of fsl,refclk-pad-mode. And, add the unused description of this property. - Add description for each register entry. - Add fsl,hsio-cfg description. - Other minor refine changes. PHY driver - To make codes safe enough in multi instances probe, use scoped_guard() to replace the atomic_###() callbacks. v4:https://patchwork.kernel.org/project/linux-phy/cover/1715234181-672-1-git-send-email-hongxing.zhu@nxp.com/ v4 changes: - Re-format the "phy-cells" as <&hsio_phy lane_id phy_mode controller_id> - Use each lane as a phys entry, suggested by Rob. PCIEA: phys = <&hsio_phy 0 PHY_MODE_PCIE>; or: phys = <&hsio_phy 0 PHY_MODE_PCIE>, <&hsio_phy 1 PHY_MODE_PCIE>; PCIEB: phys = <&hsio_phy 1 PHY_MODE_PCIE>; or: phys = <&hsio_phy 2 PHY_MODE_PCIE>; SATA: phys = <&hsio_phy 2 PHY_MODE_SATA>; - Add a new propery "fsl,hsio-cfg". The HSIO configuration (fsl,hsio-cfg) is one global state. It should be known and used to set global setting: PCIE_AB_SELECT and PHY_X1_EPCS_SEL at the begin of HSIO initialization like this listed below. +-------------------------------------------------------------+ |CRR(SYS.CSR) register|PCIAx2 and|PCIEAx1, PCIEBx1|PCIEAx2 and| | |SATA |SATA |PCIEBx1 | |---------------------|----------|----------------|-----------| |PCIE_AB_SELECT | 0 | 1 | 1 | |---------------------|----------|----------------|-----------| |PHY_X1_EPCS_SEL | 1 | 1 | 0 | +-------------------------------------------------------------+ When first PHY instance is probed, PHY driver can't get a global view of the HSIO use case and doesn't know how to set global setting: PCIE_AB_SELECT and PHYX1_EPCS_SEL. Because first PHY instance doesn't know followed PHY instance use mode. So, one property named "fsl,hsio-cfg" has to be introduced here to specify the setting of the global setting: PCIE_AB_SELECT and PHY_X1_EPCS_SEL. Here is the discussion about this. https://lkml.org/lkml/2024/4/26/231 - Address Conor's comments about the "fsl,refclk-pad-mode". fsl,refclk-pad-mode: description: ... enum: ["input", "output"]. v3:https://patchwork.kernel.org/project/linux-phy/cover/1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com/ v3 changes: Refer to Conor's comments. - Let filename match a compatible - Refine description of the fsl,refclk-pad-mode. - Remove power-domains description. - Keep clock ording for two devices. - Drop the unused label and status. Refer to Rob's comments. - Use standard phy mode defines. - Correct the spell mistakes in the binding document. v2:https://patchwork.kernel.org/project/linux-phy/cover/1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com/ v2 changes: - Place the dt-bindings header file changes as the first one in the patch-set, make the annotation more clear, and add Frank's Reviewed-by tag. v1:https://patchwork.kernel.org/project/linux-phy/cover/1711699790-16494-1-git-send-email-hongxing.zhu@nxp.com/ [PATCH v5 1/2] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding [PATCH v5 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml | 152 +++++++++++++++++++++ drivers/phy/freescale/Kconfig | 8 ++ drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 608 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/dt-bindings/phy/phy-imx8-pcie.h | 29 ++++ 5 files changed, 798 insertions(+)