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S32G2/S32G3 includes two system eDMA instances based on v3 version, each of them integrated with 2 DMAMUX blocks. Another particularity of these SoCs is that the interrupts are shared between channels as follows: - DMA Channels 0-15 share the 'tx-0-15' interrupt - DMA Channels 16-31 share the 'tx-16-31' interrupt - all channels share the 'err' interrupt Changes in V3: - Added changelog. Changes in V2: - Added new lines in commit description. - Added "Reviewed-by" tag where received. - Removed the three commits: "dmaengine: fsl-edma: move eDMAv2 related registers to a new structure ’edma2_regs’" "dmaengine: fsl-edma: add eDMAv3 registers to edma_regs" "dmaengine: fsl-edma: wait until no hardware request is in progress". I will send a different patchset for them. Larisa Grigore (5): dmaengine: fsl-edma: select of_dma_xlate based on the dmamuxs presence dmaengine: fsl-edma: remove FSL_EDMA_DRV_SPLIT_REG check when parsing muxbase dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string dmaengine: fsl-edma: add support for S32G based platforms dmaengine: fsl-edma: read/write multiple registers in cyclic transactions .../devicetree/bindings/dma/fsl,edma.yaml | 34 ++++++ drivers/dma/fsl-edma-common.c | 36 ++++-- drivers/dma/fsl-edma-common.h | 3 + drivers/dma/fsl-edma-main.c | 115 +++++++++++++++++- 4 files changed, 173 insertions(+), 15 deletions(-)