| Message ID | 1718675485-25316-1-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | LF-12487 arm64: dts: Fix i.MX95 PCIe EP functions broken | expand |
> -----Original Message----- > From: Richard Zhu <hongxing.zhu@nxp.com> > Sent: 2024年6月18日 9:51 > To: Frank Li <frank.li@nxp.com> > Cc: imx@lists.linux.dev; Hongxing Zhu <hongxing.zhu@nxp.com> Sorry, CC to wrong mail-list. Please ignore this topic. Best Regards Richard Zhu > Subject: [PATCH] LF-12487 arm64: dts: Fix i.MX95 PCIe EP functions broken > > RC can only read out "0xFFFFFFFF" from memory regions specified by EP's BARs. > Root-cause: the memory read issued from RC to access the EP's BARs are blocked > by IOMMU of EP side. > > When PCIe EP mode is enabled, disable the SMMU at EP side to fix it. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso > b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso > index 9c5c46a281ef8..cc1a3cd74212c 100644 > --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso > +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso > @@ -6,6 +6,11 @@ > /dts-v1/; > /plugin/; > > +&smmu { > + status = "disabled"; > +}; > + > + > &pcie1 { > status = "disabled"; > }; > -- > 2.37.1
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso index 9c5c46a281ef8..cc1a3cd74212c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso @@ -6,6 +6,11 @@ /dts-v1/; /plugin/; +&smmu { + status = "disabled"; +}; + + &pcie1 { status = "disabled"; };
RC can only read out "0xFFFFFFFF" from memory regions specified by EP's BARs. Root-cause: the memory read issued from RC to access the EP's BARs are blocked by IOMMU of EP side. When PCIe EP mode is enabled, disable the SMMU at EP side to fix it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso | 5 +++++ 1 file changed, 5 insertions(+)