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b=fVC+mX3my1/9ddGYeePvln57/uAcIN6NF8THGW97qyxmfJaoVztMAAsljquFGn3+zQZOVompIIzZ6bv88AbNuQdoJkE1w1C+gcliAWlcvwpVGOTvLXx6Lh3QRYW9YLEazsUv+GHrfh5Kc6X0K1/gtKVBl2mW6F/CyRAgwvnZUa4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by DU2PR04MB8504.eurprd04.prod.outlook.com (2603:10a6:10:2d3::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.38; Thu, 7 Mar 2024 09:57:45 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Thu, 7 Mar 2024 09:57:45 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v6 4/7] perf: imx_perf: refactor driver for imx93 Date: Thu, 7 Mar 2024 17:57:27 +0800 Message-Id: <20240307095730.3792680-4-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307095730.3792680-1-xu.yang_2@nxp.com> References: <20240307095730.3792680-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SG2PR06CA0212.apcprd06.prod.outlook.com (2603:1096:4:68::20) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|DU2PR04MB8504:EE_ X-MS-Office365-Filtering-Correlation-Id: fcb989cd-d345-4614-5c0e-08dc3e8d0993 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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However, some macro definitions and events are different on these two Socs. For preparing imx95 supports, this will refactor driver for imx93. Signed-off-by: Xu Yang --- Changes in v4: - new patch Changes in v5: - use is_visible to hide unwanted attributes as suggested by Will Changes in v6: - improve imx93_ddr_perf_monitor_config() --- drivers/perf/fsl_imx9_ddr_perf.c | 99 +++++++++++++++++++++----------- 1 file changed, 66 insertions(+), 33 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 8d85b4d98544..4e8a3a4349c5 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -11,14 +11,14 @@ #include /* Performance monitor configuration */ -#define PMCFG1 0x00 -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) -#define PMCFG1_RD_BT_FILT_EN BIT(29) -#define PMCFG1_ID_MASK GENMASK(17, 0) +#define PMCFG1 0x00 +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) -#define PMCFG2 0x04 -#define PMCFG2_ID GENMASK(17, 0) +#define PMCFG2 0x04 +#define MX93_PMCFG2_ID GENMASK(17, 0) /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 @@ -77,6 +77,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .identifier = "imx93", }; +static inline bool is_imx93(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx93_devtype_data; +} + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, { /* sentinel */ } @@ -186,7 +191,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/ /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), @@ -198,7 +203,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/ /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), @@ -210,7 +215,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/ /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), @@ -245,9 +250,26 @@ static struct attribute *ddr_perf_events_attrs[] = { NULL, }; +static umode_t +ddr_perf_events_attrs_is_visible(struct kobject *kobj, + struct attribute *attr, int unused) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); + + if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") || + !strcmp(attr->name, "eddrtq_pm_wr_trans_filt") || + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) && + !is_imx93(ddr_pmu)) + return 0; + + return attr->mode; +} + static const struct attribute_group ddr_perf_events_attr_group = { .name = "events", .attrs = ddr_perf_events_attrs, + .is_visible = ddr_perf_events_attrs_is_visible, }; PMU_FORMAT_ATTR(event, "config:0-15"); @@ -369,36 +391,47 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, } } -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, - int counter, int axi_id, int axi_mask) +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, + int counter, int axi_id, int axi_mask) { u32 pmcfg1, pmcfg2; pmcfg1 = readl_relaxed(pmu->base + PMCFG1); - if (counter == 2 && event == 73) - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; - else if (counter == 2 && event != 73) - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; - - if (counter == 3 && event == 73) - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; - else if (counter == 3 && event != 73) - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; - - if (counter == 4 && event == 73) - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; - else if (counter == 4 && event != 73) - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; + if (event == 73) { + switch (counter) { + case 2: + pmcfg1 |= MX93_PMCFG1_RD_TRANS_FILT_EN; + break; + case 3: + pmcfg1 |= MX93_PMCFG1_WR_TRANS_FILT_EN; + break; + case 4: + pmcfg1 |= MX93_PMCFG1_RD_BT_FILT_EN; + break; + } + } else { + switch (counter) { + case 2: + pmcfg1 &= ~MX93_PMCFG1_RD_TRANS_FILT_EN; + break; + case 3: + pmcfg1 &= ~MX93_PMCFG1_WR_TRANS_FILT_EN; + break; + case 4: + pmcfg1 &= ~MX93_PMCFG1_RD_BT_FILT_EN; + break; + } + } - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask); - writel(pmcfg1, pmu->base + PMCFG1); + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask); + writel_relaxed(pmcfg1, pmu->base + PMCFG1); pmcfg2 = readl_relaxed(pmu->base + PMCFG2); - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); - pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id); - writel(pmcfg2, pmu->base + PMCFG2); + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF); + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id); + writel_relaxed(pmcfg2, pmu->base + PMCFG2); } static void ddr_perf_event_update(struct perf_event *event) @@ -514,7 +547,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) ddr_perf_event_start(event, flags); /* read trans, write trans, read beat */ - ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); + imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); return 0; }